From patchwork Thu Nov 30 16:39:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120225 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp14195qgn; Thu, 30 Nov 2017 08:40:43 -0800 (PST) X-Google-Smtp-Source: AGs4zMbgJpSvjpRH+gmGQo32Mqgkf/0L20TPL/hSwNcSPkzhmikci7Fh0ax+L5CR2ESgyGk84IR4 X-Received: by 10.159.249.1 with SMTP id bf1mr3208226plb.401.1512060043822; Thu, 30 Nov 2017 08:40:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512060043; cv=none; d=google.com; s=arc-20160816; b=CDJ1mwj6YaD3S8bjpBp8iS3L+qYeDsF9bF6KuKr+DkSREfO6f5eSd8COi8DJCkBW8K Yij7B9iXqpIiInioUFH1aUb5vF/B94h5C8SthS69Il220T4FnEPsYyxCW5v5DWP9ynN5 uCAroJIJMAy7qHy4K2h8MkVsIfwoeZaHuKYymMzIk1+iK9XRQ9ZC4enJ5UP7iLHusvik qtW04dOEzzK6QMDUgGuXun5SmvIlRa2b3Smug6SU0lqSwrWtL4F/ccSDiolCgsNenwKU otMN2kjvfaWnICByCmknAYwoPA+l4TIMcjPYWAvbY4pFHwAIDrhSP+soSTaF+fnmMWxM grJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=aH7JQKGvfCSRiFksL2Cp4GDO2T3Y52614K79dFdZ96Y=; b=aHBJhIHtWYQgbsAJ/6U3curGyxt7a3KFVtxg8VWhuOXn9TanNLr/6mewScRgqHRBcG Qo1AjnKugBvYqx8WfmKFm5I2BuZSY8W2F9g+2+F9qu6S1g0mXXn2rPom1b2Z4PcEYv4s RkUHPrHLy7RT/Y6SnhYLuNRIzOC/hR1Nt6sj8iJeH7nRuW7w0TwFa3fMOWdvFfhHg4ZL i1o6tRCqnd6V4s8zofhx0Hm7OCZ96TcKVH7mRj7wbxscbdAVKRXzWZ6CynSx5oioJ5v7 /9sxxkWhiUyObrIaM4BhuOsLlHe1lYKp5m70jOkYPJc9j16PcBCdLb0U+IzdaaYq/LWm LIyw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h72si3532928pfj.20.2017.11.30.08.40.43; Thu, 30 Nov 2017 08:40:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753510AbdK3Qkk (ORCPT + 28 others); Thu, 30 Nov 2017 11:40:40 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:57574 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753357AbdK3Qjr (ORCPT ); Thu, 30 Nov 2017 11:39:47 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A317C1A25; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 74BF63F774; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 5456C1AE3DFC; Thu, 30 Nov 2017 16:39:48 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v2 14/18] arm64: erratum: Work around Falkor erratum #E1003 in trampoline code Date: Thu, 30 Nov 2017 16:39:42 +0000 Message-Id: <1512059986-21325-15-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512059986-21325-1-git-send-email-will.deacon@arm.com> References: <1512059986-21325-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We rely on an atomic swizzling of TTBR1 when transitioning from the entry trampoline to the kernel proper on an exception. We can't rely on this atomicity in the face of Falkor erratum #E1003, so on affected cores we can issue a TLB invalidation to invalidate the walk cache prior to jumping into the kernel. There is still the possibility of a TLB conflict here due to conflicting walk cache entries prior to the invalidation, but this doesn't appear to be the case on these CPUs in practice. Signed-off-by: Will Deacon --- arch/arm64/Kconfig | 17 +++++------------ arch/arm64/kernel/entry.S | 10 ++++++++++ 2 files changed, 15 insertions(+), 12 deletions(-) -- 2.1.4 diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a93339f5178f..fdcc7b9bb15d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -522,20 +522,13 @@ config CAVIUM_ERRATUM_30115 config QCOM_FALKOR_ERRATUM_1003 bool "Falkor E1003: Incorrect translation due to ASID change" default y - select ARM64_PAN if ARM64_SW_TTBR0_PAN help On Falkor v1, an incorrect ASID may be cached in the TLB when ASID - and BADDR are changed together in TTBRx_EL1. The workaround for this - issue is to use a reserved ASID in cpu_do_switch_mm() before - switching to the new ASID. Saying Y here selects ARM64_PAN if - ARM64_SW_TTBR0_PAN is selected. This is done because implementing and - maintaining the E1003 workaround in the software PAN emulation code - would be an unnecessary complication. The affected Falkor v1 CPU - implements ARMv8.1 hardware PAN support and using hardware PAN - support versus software PAN emulation is mutually exclusive at - runtime. - - If unsure, say Y. + and BADDR are changed together in TTBRx_EL1. Since we keep the ASID + in TTBR1_EL1, this situation only occurs in the entry trampoline and + then only for entries in the walk cache, since the leaf translation + is unchanged. Work around the erratum by invalidating the walk cache + entries for the trampoline before entering the kernel proper. config QCOM_FALKOR_ERRATUM_1009 bool "Falkor E1009: Prematurely complete a DSB after a TLBI" diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 99d105048663..a5ec6ab5c711 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -989,6 +989,16 @@ __ni_sys_trace: sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE) bic \tmp, \tmp, #USER_ASID_FLAG msr ttbr1_el1, \tmp +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003 + movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12) + movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12) + movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & (SZ_2M - 1)) >> 12) + isb + tlbi vae1, \tmp + dsb nsh +alternative_else_nop_endif +#endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ .endm .macro tramp_unmap_kernel, tmp