From patchwork Thu Nov 30 16:39:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120226 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp14468qgn; Thu, 30 Nov 2017 08:40:56 -0800 (PST) X-Google-Smtp-Source: AGs4zMah2TONTi90WQQlIR7jmZ8JCKDvgAbCT6UiNsCRurXArST9v1WyusrRVpdzecLrqGcIeiWq X-Received: by 10.99.134.73 with SMTP id x70mr2985999pgd.130.1512060056242; Thu, 30 Nov 2017 08:40:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512060056; cv=none; d=google.com; s=arc-20160816; b=zBYGcbVGm6NNBZ9F2dWPPldtpanbGS2imUeWyX0vCiJVc+7W/ycDMYREhXZygJZ/LI JLbXpGlOWHhIAmACmbQvXyvKtSBC+VUaH+G3g/A7Bnofevt0rHUYneBnPNR0/h5gPyzE FFm5GgKbF2qv4vZYpkMhXNzu97Ce7lQYyXNgdgQYLTCQGb4gxLa5eB+z/dGbOpFeS1wY pVpbZe66mG9tWbIXi5o7u5sxjOavLpk6Ete5JRhAWSEbqx4Y7aLDwXLIsaZonvbWHnkD bulAiAbvAn2WLFU8LR9tvNCl2oOQyFeEsLj+dfK9ZEGwDgZT9sgvIERj8ymLjMBPmyqv 72ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=tGwqIzaw6YVQZJvN26AWqQo/vaSJU0HHNefiNUooruk=; b=LURDOf+vwdSIIDyZKRyNgD5mAlPEf1gWSqk/+r96ESvEE5/+/vPab03FQ7Cw/JqEYd qt4WRLsZuhdret9Cu/fMTbdo2qgoFeCcbiAcMQvAB5u008Pii1+mVWbkPsTH6PI3hwPp PYRgXN+/8GHx0jiowEzIXzaffe6wEhv+n3N8inxeBryXWXvw4iaYfypXRalZgZkKCpgw zCE6q+PkSZJCRLMPR2rWZD1ZvktYXD+qpAlI8NIGMRKfEmO7OzWz+riqHdr66x19FXzw hXwfoy+YDDoRrfxpbMkAr3pMAVjbHt1HHA7rQ0g+fX+x5IAng+lv5Rz2wDs3grxiV1Xr 2DEg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h72si3532928pfj.20.2017.11.30.08.40.55; Thu, 30 Nov 2017 08:40:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753496AbdK3Qkj (ORCPT + 28 others); Thu, 30 Nov 2017 11:40:39 -0500 Received: from foss.arm.com ([217.140.101.70]:57482 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753366AbdK3Qjr (ORCPT ); Thu, 30 Nov 2017 11:39:47 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BF5681A9A; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8FF593F7C3; Thu, 30 Nov 2017 08:39:45 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 600031AE3DFD; Thu, 30 Nov 2017 16:39:48 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v2 15/18] arm64: tls: Avoid unconditional zeroing of tpidrro_el0 for native tasks Date: Thu, 30 Nov 2017 16:39:43 +0000 Message-Id: <1512059986-21325-16-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512059986-21325-1-git-send-email-will.deacon@arm.com> References: <1512059986-21325-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When unmapping the kernel at EL0, we use tpidrro_el0 as a scratch register during exception entry from native tasks and subsequently zero it in the kernel_ventry macro. We can therefore avoid zeroing tpidrro_el0 in the context-switch path for native tasks using the entry trampoline. Signed-off-by: Will Deacon --- arch/arm64/kernel/process.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) -- 2.1.4 diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index b2adcce7bc18..aba3a1fb492d 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -361,16 +361,14 @@ void tls_preserve_current_state(void) static void tls_thread_switch(struct task_struct *next) { - unsigned long tpidr, tpidrro; - tls_preserve_current_state(); - tpidr = *task_user_tls(next); - tpidrro = is_compat_thread(task_thread_info(next)) ? - next->thread.tp_value : 0; + if (is_compat_thread(task_thread_info(next))) + write_sysreg(next->thread.tp_value, tpidrro_el0); + else if (!arm64_kernel_unmapped_at_el0()) + write_sysreg(0, tpidrro_el0); - write_sysreg(tpidr, tpidr_el0); - write_sysreg(tpidrro, tpidrro_el0); + write_sysreg(*task_user_tls(next), tpidr_el0); } /* Restore the UAO state depending on next's addr_limit */