From patchwork Wed Dec 6 12:35:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120829 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7001012qgn; Wed, 6 Dec 2017 04:37:49 -0800 (PST) X-Google-Smtp-Source: AGs4zMZ3yq+byTqhnt/unzOwhlUe6L203zAto0qCkwX0FcZEfxC1AwK4NfpwKn3Y0kxxJC19QokB X-Received: by 10.99.150.9 with SMTP id c9mr20887449pge.386.1512563869732; Wed, 06 Dec 2017 04:37:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512563869; cv=none; d=google.com; s=arc-20160816; b=VHA8bw2Y1hnipqbpI251Qot7zu0g/QfvwJ38wBWs0FfUNMgXHeiS3zJ6ZoGXdOxwSF Vkpmb6ypV0YKNBDBKLyC+XxruieuTe6hgUER7f73wftPUkWhYNkIm8ZU9ASsrk4ypl2p ezkovq8x7WI+VbjwDuwhEapFEvTlCKEcwhUVmzphfx+4zXBUVJmkdEnXcUcQL3Gbyxd8 5sWdIhk3IAYoBMf7QStUjUFO6FE2+wXWvYA+s4bEH8/mlGm8WXzMAdlvYxlfnKybClu3 JPtoK+uSed2nOs1kKhM8MtnnKoYfTffpourXwVS21v+6xJgFSdFA63EanenIImlg3C1I ynFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=MWK0I+38g9PduFq3oPJBrEnulhT3e5DtfUfQUVA9k3Y=; b=DsZYB0VSBTXU1P3nwC0FHxZRn9O8weLGs/mM1npV5Ar0V5bvLS3XDHUROWgWXz+zue cSS+PUXHg7RpYUSP2OzFk4sGJdBmJrVeZ98hi/DxDGScXqCBy7P3PaqGwOdKQJ9BiXu8 GGFTOeDe7es8xMscxgUz5otnvRKR+5igHVX+LulVhGDFM+DnH7MWVYrxyE8aDcT5Bq1j 29YzTg6i7QRENZncHzRG64m60Te519VnZ70LfcsAdXVVYsVwuFnPM3uyWbF6UjNwtybU T+Rhq7FYGipo713QsL+bHBpbsWQ5YueqDExChdpIXw6cX/WEK9M9xIayIz7P/ERt8Dzk Roaw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s59si1910014plb.232.2017.12.06.04.37.49; Wed, 06 Dec 2017 04:37:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752606AbdLFMhq (ORCPT + 28 others); Wed, 6 Dec 2017 07:37:46 -0500 Received: from foss.arm.com ([217.140.101.70]:34694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751709AbdLFMgN (ORCPT ); Wed, 6 Dec 2017 07:36:13 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D80541993; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A9F753F53E; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 322CC1AE3632; Wed, 6 Dec 2017 12:36:17 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v3 19/20] arm64: mm: Introduce TTBR_ASID_MASK for getting at the ASID in the TTBR Date: Wed, 6 Dec 2017 12:35:38 +0000 Message-Id: <1512563739-25239-20-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512563739-25239-1-git-send-email-will.deacon@arm.com> References: <1512563739-25239-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are now a handful of open-coded masks to extract the ASID from a TTBR value, so introduce a TTBR_ASID_MASK and use that instead. Suggested-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/include/asm/asm-uaccess.h | 3 ++- arch/arm64/include/asm/mmu.h | 1 + arch/arm64/include/asm/uaccess.h | 4 ++-- arch/arm64/kernel/entry.S | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) -- 2.1.4 Reviewed-by: Mark Rutland diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index 21b8cf304028..f4f234b6155e 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -4,6 +4,7 @@ #include #include +#include #include #include @@ -17,7 +18,7 @@ msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 isb sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE - bic \tmp1, \tmp1, #(0xffff << 48) + bic \tmp1, \tmp1, #TTBR_ASID_MASK msr ttbr1_el1, \tmp1 // set reserved ASID isb .endm diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index da6f12e40714..6f7bdb89817f 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -18,6 +18,7 @@ #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ #define USER_ASID_FLAG (UL(1) << 48) +#define TTBR_ASID_MASK (UL(0xffff) << 48) #ifndef __ASSEMBLY__ diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 750a3b76a01c..6eadf55ebaf0 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -112,7 +112,7 @@ static inline void __uaccess_ttbr0_disable(void) write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); isb(); /* Set reserved ASID */ - ttbr &= ~(0xffffUL << 48); + ttbr &= ~TTBR_ASID_MASK; write_sysreg(ttbr, ttbr1_el1); isb(); } @@ -131,7 +131,7 @@ static inline void __uaccess_ttbr0_enable(void) /* Restore active ASID */ ttbr1 = read_sysreg(ttbr1_el1); - ttbr1 |= ttbr0 & (0xffffUL << 48); + ttbr1 |= ttbr0 & TTBR_ASID_MASK; write_sysreg(ttbr1, ttbr1_el1); isb(); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 5d51bdbb2131..3eabcb194c87 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -205,7 +205,7 @@ alternative_else_nop_endif .if \el != 0 mrs x21, ttbr1_el1 - tst x21, #0xffff << 48 // Check for the reserved ASID + tst x21, #TTBR_ASID_MASK // Check for the reserved ASID orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR b.eq 1f // TTBR0 access already disabled and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR