From patchwork Wed Dec 6 12:35:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 120840 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7003573qgn; Wed, 6 Dec 2017 04:40:34 -0800 (PST) X-Google-Smtp-Source: AGs4zMaBkt7cg8iIDwbB5f/YK+5HBI3J8aF/MGEzx6d+MhZ/BHbaRiTdz102i9SBnTi2+IJPoyhq X-Received: by 10.84.178.37 with SMTP id y34mr22085723plb.260.1512564034223; Wed, 06 Dec 2017 04:40:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512564034; cv=none; d=google.com; s=arc-20160816; b=sJF/mDz5bNlZ/K9qZtkGQXLvlU009ClXsXiJLjNkA9uEkfa7NZ8sqSY3bNpbIIEjoR iebOaMmIYvYb8fWxVjJ7qMXOWapatPaDO+tOGhA9mSuwsx+GhvGKOweNc48A86CF3Gvb qeWqudAOe2rUdAU8AsCKTmO1aoTuyy2b84z6OI8B3SbC2a2jFbwnDkwvOTw7wmiLmwVM YJFvcYWBlVrIU8+gggCHyIRcudgVIywfvdlHnJyNRW2OW/7amUcEwxbGkkfnnLAh6NWs fgg+OhqQBBvG/cGg4GqbVwPR9cvmf28Ap/SQLl6qetDWWzNLhd5/+bnacQ1KD5dDFlyP MTig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=xsYaxVEvIt1tMVeZ/68raCM1OvJcwsghUJ9N018ZgRU=; b=nx35OP0rj5sHy8Zt/jMLWPFS5DFTfrkDKMrS/Vx3J6LZDwbjOyUOGWNitS3cJyH34z cqNhYjQ6JN13Ys31t0nZbjo5bEoMpU3SPi074poz12tEJmM7Wd2JNXs5SfSgoutJ50dc mhnned2MhD8WeoSWuF4ziXTA4K5AyzSIUJncC9+zmijGzIc+H7hEYSJn2lg3AmIbeIOx No9y4frGKJVNJR+xQk6iOPGcvIRMSJRw1GntdzDzH1rIfKpf9kyJf3cX+T8e3LrMij03 CYiTFu5sWb4pq8vJrGIDfD0ZsVIkhlE9A+VLa/wCK65Wkwl+psp4DC3dW1MCnmQaibNu g3Rg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h8si1999757pfi.0.2017.12.06.04.40.33; Wed, 06 Dec 2017 04:40:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752601AbdLFMkc (ORCPT + 28 others); Wed, 6 Dec 2017 07:40:32 -0500 Received: from foss.arm.com ([217.140.101.70]:34694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752141AbdLFMgL (ORCPT ); Wed, 6 Dec 2017 07:36:11 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 60543165C; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3211C3F53E; Wed, 6 Dec 2017 04:36:11 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 1644D1AE3719; Wed, 6 Dec 2017 12:36:16 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, ard.biesheuvel@linaro.org, sboyd@codeaurora.org, dave.hansen@linux.intel.com, keescook@chromium.org, msalter@redhat.com, labbott@redhat.com, tglx@linutronix.de, Will Deacon Subject: [PATCH v3 05/20] arm64: mm: Rename post_ttbr0_update_workaround Date: Wed, 6 Dec 2017 12:35:24 +0000 Message-Id: <1512563739-25239-6-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1512563739-25239-1-git-send-email-will.deacon@arm.com> References: <1512563739-25239-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The post_ttbr0_update_workaround hook applies to any change to TTBRx_EL1. Since we're using TTBR1 for the ASID, rename the hook to make it clearer as to what it's doing. Reviewed-by: Mark Rutland Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 5 ++--- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/proc.S | 2 +- 3 files changed, 4 insertions(+), 5 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index e1fa5db858b7..c45bc94f15d0 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -477,10 +477,9 @@ alternative_endif .endm /* -/* - * Errata workaround post TTBR0_EL1 update. + * Errata workaround post TTBRx_EL1 update. */ - .macro post_ttbr0_update_workaround + .macro post_ttbr_update_workaround #ifdef CONFIG_CAVIUM_ERRATUM_27456 alternative_if ARM64_WORKAROUND_CAVIUM_27456 ic iallu diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 6d14b8f29b5f..804e43c9cb0b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -257,7 +257,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr0_update_workaround + post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index f2ff0837577c..3146dc96f05b 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,7 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr0_update_workaround + post_ttbr_update_workaround ret ENDPROC(cpu_do_switch_mm)