From patchwork Fri Jan 5 13:12:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123518 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp801073qgn; Fri, 5 Jan 2018 05:13:43 -0800 (PST) X-Google-Smtp-Source: ACJfBovez6r65cIrbai047Wtx+aDgyhOXk5q0I7wwshWNxdsLS6+ekL1e0U8WYuRpD6NKZ7ba7qO X-Received: by 10.98.133.137 with SMTP id m9mr2903012pfk.97.1515158023318; Fri, 05 Jan 2018 05:13:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515158023; cv=none; d=google.com; s=arc-20160816; b=gAuHLKBwERpZUKe923b5ObP/SsJwnHQia53ZwKhyr994giiccMz9H4uCJ/nMcPSTOZ wiuyLi4Kem0pJH94BiPq3xchyxQ4MXhHcMoVV/rF7znoeIvqKiODgRnhoRWlNp5uFqvG w0MFNgUfV+TOKMDrmbZxQHr9B4ntcBPLFnM/J3lmU2/kx7nXjp0SbgezVdT28725FBkX YWRyOJnFP9NtcW1p4hL1kQxvICZt66ctUUYGmBXd7ejsaW1Qq9q4GRIC8G50lODBTYPP xSfV7KxEuFaB7logqzyKB616pKfFBom0bE8VdjdXFd+s7gzLIk1Gw3E9E+MjKyX2PpzY uikg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=jpUYmNEx7VU+s0l/ndx3SHVIXhCGbNw/RkyqJRiZOVc=; b=GljKerlRrwDXHd1p28VLSSQQUGeAmbAs3EXtApGEE1TTcloZ+2Kk2n7hPdrbr9XRGl AwIUBt7l3hHbL7VCwPAhVjf1TawGnIm96W4hUGjM5qfxccusxDlJcQ9oLEPmGxNCOz82 gyT+TIiqxyTs1KX8MkQB5e9tTQx+3lJLl0LmfZhezUtgohgRbFQ4suipL7FFkRBDM6m/ PL3nUd0xVf+lRiqZkDGlpFRI6QBsutPKWW8UuAGAcP3BE1ElNj05RVjqHIq3bO+g6YKO Z6NAa3ONiOmj8j/bO9YRP4SnvtHTvq+YF9gCi9QpAvr2PHrD9qMa/hM6yE0RjXKoxLtC hFpg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w24si3923319plp.808.2018.01.05.05.13.43; Fri, 05 Jan 2018 05:13:43 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751970AbeAENNQ (ORCPT + 27 others); Fri, 5 Jan 2018 08:13:16 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44790 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751646AbeAENMo (ORCPT ); Fri, 5 Jan 2018 08:12:44 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CECB5169E; Fri, 5 Jan 2018 05:12:43 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9DB8D3F7C5; Fri, 5 Jan 2018 05:12:43 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 8C2B71AE2FF7; Fri, 5 Jan 2018 13:12:43 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, labbott@redhat.com, Will Deacon Subject: [PATCH v2 10/11] arm64: cputype: Add missing MIDR values for Cortex-A72 and Cortex-A75 Date: Fri, 5 Jan 2018 13:12:40 +0000 Message-Id: <1515157961-20963-11-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515157961-20963-1-git-send-email-will.deacon@arm.com> References: <1515157961-20963-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hook up MIDR values for the Cortex-A72 and Cortex-A75 CPUs, since they will soon need MIDR matches for hardening the branch predictor. Signed-off-by: Will Deacon --- arch/arm64/include/asm/cputype.h | 4 ++++ 1 file changed, 4 insertions(+) -- 2.1.4 diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d98261..84385b94e70b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -79,8 +79,10 @@ #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 #define ARM_CPU_PART_CORTEX_A57 0xD07 +#define ARM_CPU_PART_CORTEX_A72 0xD08 #define ARM_CPU_PART_CORTEX_A53 0xD03 #define ARM_CPU_PART_CORTEX_A73 0xD09 +#define ARM_CPU_PART_CORTEX_A75 0xD0A #define APM_CPU_PART_POTENZA 0x000 @@ -94,7 +96,9 @@ #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) +#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +#define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)