From patchwork Fri Jan 5 13:12:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123524 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp802553qgn; Fri, 5 Jan 2018 05:15:09 -0800 (PST) X-Google-Smtp-Source: ACJfBosmqn2pclZ1vhMJ1Nl3ojzAC3uwwpscHAwzsDBzKCNUvFG1QikvM2xsLCYuPjWip0SKtlRT X-Received: by 10.159.242.198 with SMTP id x6mr3093437plw.85.1515158109252; Fri, 05 Jan 2018 05:15:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515158109; cv=none; d=google.com; s=arc-20160816; b=t4hpPJQJMZ6nheTA+L87Ig6/bJrdvlxdZFXE1qKVa6eiuiHDBx0xoTTUigkdC53iyu H+1QKjcI/8aCZb1Xi/RjsMPlcJkU97WAVeURM0B1VMX0k4J2G5vvDBfDp042KBx1TH61 DHNJlnfO7zkys/fZLMei3aCc9VKG35PQN8fpwbSjiryHgw6kSXrJIaI7Zi/Zp8i3iPf5 T9b4mG1ni+UBUe0L+qTS4jQelwqH8/stkig4CTCdMh6Z6yf5ldDopbdtQVYpLprF/jBP bAGUZ8iwlh0yyJ0ohNotHBPmqYAs1RloXbpR/+FvW5/ZuNYd4WMK6o65Uaix6z+N5I4K XZaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=XxJIX19e1/CLyfFspwtK0ieb7ju70HgiknwjiyE2oH0=; b=o4MDjMCnOEHgdQAfB+uCDBEtQSBXt2IdmoYBYHX1znAxtXqYgK7+wfZZ8SDSaAfe2L CRsCp2XsnSxl4m2PwuDIONm0UFpQznxAblHs6PYQ7E9MDCNdeRynHgTnTnKLQ/JBoh3h izxjN3SE9KpsoAZ/sZAvXoMCCOVuspP6heXwTcqibDTEJ5aiPuWBJNizww63Woqk1mja XSPqD1m6YMaQJElhYnU5iHpOBaok1HKlxo/wLthW1aepEwzxV9PVTDNFcTuGusKVwwyu 8RMR1E5pYXS5jOY3o50aMPzEy3OiwVB7I28Nrxx/GBIgGAdmxxpqQ/nxlVeUWMYvEPGo sm8Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z6si4033614pfi.345.2018.01.05.05.15.08; Fri, 05 Jan 2018 05:15:09 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752008AbeAENOX (ORCPT + 27 others); Fri, 5 Jan 2018 08:14:23 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:44776 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751551AbeAENMn (ORCPT ); Fri, 5 Jan 2018 08:12:43 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6EF2165D; Fri, 5 Jan 2018 05:12:43 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 829C83F6CF; Fri, 5 Jan 2018 05:12:43 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 4BF511AE2D78; Fri, 5 Jan 2018 13:12:43 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, labbott@redhat.com, Will Deacon Subject: [PATCH v2 06/11] arm64: Move post_ttbr_update_workaround to C code Date: Fri, 5 Jan 2018 13:12:36 +0000 Message-Id: <1515157961-20963-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515157961-20963-1-git-send-email-will.deacon@arm.com> References: <1515157961-20963-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 13 ------------- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index c45bc94f15d0..cee60ce0da52 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -476,17 +476,4 @@ alternative_endif mrs \rd, sp_el0 .endm -/* - * Errata workaround post TTBRx_EL1 update. - */ - .macro post_ttbr_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 71092ee09b6b..62500d371b06 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -277,7 +277,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr_update_workaround + bl post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 1cb3bc92ae5c..5f7097d0cd12 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -239,6 +239,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 3146dc96f05b..6affb68a9a14 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,8 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"