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[209.132.180.67]) by mx.google.com with ESMTP id x13si6929905pfk.293.2018.01.07.04.16.13; Sun, 07 Jan 2018 04:16:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753885AbeAGMQJ (ORCPT + 28 others); Sun, 7 Jan 2018 07:16:09 -0500 Received: from foss.arm.com ([217.140.101.70]:57410 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752944AbeAGMQI (ORCPT ); Sun, 7 Jan 2018 07:16:08 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E9A71435; Sun, 7 Jan 2018 04:16:08 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 679FA3F581; Sun, 7 Jan 2018 04:16:06 -0800 (PST) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Ofir Drang , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Subject: [PATCH v3 03/27] staging: ccree: fold reg common defines into driver Date: Sun, 7 Jan 2018 12:14:14 +0000 Message-Id: <1515327285-8948-4-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515327285-8948-1-git-send-email-gilad@benyossef.com> References: <1515327285-8948-1-git-send-email-gilad@benyossef.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fold the 2 macro defined in dx_reg_common.h into the file they are used in and delete the file. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_crypto_ctx.h | 4 ++-- drivers/staging/ccree/dx_reg_common.h | 13 ------------- drivers/staging/ccree/ssi_driver.h | 5 +++-- 3 files changed, 5 insertions(+), 17 deletions(-) delete mode 100644 drivers/staging/ccree/dx_reg_common.h -- 2.7.4 diff --git a/drivers/staging/ccree/cc_crypto_ctx.h b/drivers/staging/ccree/cc_crypto_ctx.h index 02e14f3..eb16842 100644 --- a/drivers/staging/ccree/cc_crypto_ctx.h +++ b/drivers/staging/ccree/cc_crypto_ctx.h @@ -8,7 +8,7 @@ /* context size */ #ifndef CC_CTX_SIZE_LOG2 -#if (CC_SUPPORT_SHA > 256) +#if (CC_DEV_SHA_MAX > 256) #define CC_CTX_SIZE_LOG2 8 #else #define CC_CTX_SIZE_LOG2 7 @@ -59,7 +59,7 @@ #define CC_SHA384_BLOCK_SIZE 128 #define CC_SHA512_BLOCK_SIZE 128 -#if (CC_SUPPORT_SHA > 256) +#if (CC_DEV_SHA_MAX > 256) #define CC_DIGEST_SIZE_MAX CC_SHA512_DIGEST_SIZE #define CC_HASH_BLOCK_SIZE_MAX CC_SHA512_BLOCK_SIZE /*1024b*/ #else /* Only up to SHA256 */ diff --git a/drivers/staging/ccree/dx_reg_common.h b/drivers/staging/ccree/dx_reg_common.h deleted file mode 100644 index 76c5539..0000000 --- a/drivers/staging/ccree/dx_reg_common.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */ - -#ifndef __CC_REG_COMMON_H__ -#define __CC_REG_COMMON_H__ - -#define CC_DEV_SIGNATURE 0xDCC71200UL - -#define CC_HW_VERSION 0xef840015UL - -#define CC_DEV_SHA_MAX 512 - -#endif /*__CC_REG_COMMON_H__*/ diff --git a/drivers/staging/ccree/ssi_driver.h b/drivers/staging/ccree/ssi_driver.h index df805db..60c1cfd 100644 --- a/drivers/staging/ccree/ssi_driver.h +++ b/drivers/staging/ccree/ssi_driver.h @@ -27,8 +27,7 @@ /* Registers definitions from shared/hw/ree_include */ #include "dx_host.h" -#include "dx_reg_common.h" -#define CC_SUPPORT_SHA CC_DEV_SHA_MAX +#define CC_DEV_SHA_MAX 512 #include "cc_crypto_ctx.h" #include "cc_hw_queue_defs.h" #include "ssi_sram_mgr.h" @@ -44,6 +43,8 @@ extern bool cc_dump_bytes; /* Maximum DMA mask supported by IP */ #define DMA_BIT_MASK_LEN 48 +#define CC_DEV_SIGNATURE 0xDCC71200UL + #define CC_AXI_IRQ_MASK ((1 << CC_AXIM_CFG_BRESPMASK_BIT_SHIFT) | \ (1 << CC_AXIM_CFG_RRESPMASK_BIT_SHIFT) | \ (1 << CC_AXIM_CFG_INFLTMASK_BIT_SHIFT) | \