From patchwork Mon Jan 8 17:32:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 123759 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp3003579qgn; Mon, 8 Jan 2018 09:34:57 -0800 (PST) X-Google-Smtp-Source: ACJfBovLb9bDriqV/x+O1aFRv/k/l79NFhTMWhEW3QwQXB/TR3qduXS+NTnsg5gKZ7NTKXDnCQ4P X-Received: by 10.98.209.68 with SMTP id t4mr11247059pfl.153.1515432896977; Mon, 08 Jan 2018 09:34:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1515432896; cv=none; d=google.com; s=arc-20160816; b=DyPoxwEU/8KE6VL83y2nJWg4oCweQ9YpW95mWSo7eXPD4YPH7dJSKasVd1OVxnJNQr w1x0nbZmk4kQKdfToFOvId/bnn8Mq7XcK6qg+Eipc7gSIdQKbjapt0H9FEI3cucmbMZo x6Of3ogUOedguUCUWsA/ovSFWJlTjbE0M/vjRN3TkdRZx4NgWrwcx1WWc2ms5bq/lOpd 0NPLqm8McjicV0Uri/qE2aLakImieKdKM1ZBavfoBNf+LvmBplIuBzj98FEOjbE07xoo /rgXWmmfy5lnf8l/USXJUBfDeN/5D0DTXrMDoHQzU/r4zwevNhKNMGkTsWUfukdHpuc9 s9FA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=yFQDTft6/RL4dIabdCeNCsonq6RQLdzpkg7r9J54tiM=; b=y89GRPq/hpx9UxCbq0gWrQSad5ZtqpDfZCNzolqzjMG+M6ktt2u0qqj8NX5mBm0h9D SAFLwj43PsxuWOJ4DgFjqGA3ikWoNbGxwBDCapPqPqPg4TNEJiJZ32feEzCmmXvHvEVQ yVa8U0Sfe1w9NnB4byIVFc5/X2WJRLg+Mmv6e91LSe9r15XowYVsOAjS8lJg0tmT+EUq /4md7bcmoquaOmmF36kgDY2FoJqyG3+e5rlpGQBgK1BeCM2J1b5hWtZKIo4qLYFYr6Rv zt1o+6EQBs/xLfVFLak+scpA4QXJXaal3AICCj6Yu/N6QGh8N0u26NkwldTkw/7KQar2 72kA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z20si2262757pfj.118.2018.01.08.09.34.56; Mon, 08 Jan 2018 09:34:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754693AbeAHRex (ORCPT + 28 others); Mon, 8 Jan 2018 12:34:53 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:42894 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754297AbeAHRck (ORCPT ); Mon, 8 Jan 2018 12:32:40 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 22BA7169E; Mon, 8 Jan 2018 09:32:40 -0800 (PST) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E84723F5AF; Mon, 8 Jan 2018 09:32:39 -0800 (PST) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 4B8B91AE2DD9; Mon, 8 Jan 2018 17:32:41 +0000 (GMT) From: Will Deacon To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, ard.biesheuvel@linaro.org, marc.zyngier@arm.com, lorenzo.pieralisi@arm.com, christoffer.dall@linaro.org, linux-kernel@vger.kernel.org, shankerd@codeaurora.org, jnair@caviumnetworks.com, Will Deacon Subject: [PATCH v3 06/13] arm64: Move post_ttbr_update_workaround to C code Date: Mon, 8 Jan 2018 17:32:31 +0000 Message-Id: <1515432758-26440-7-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515432758-26440-1-git-send-email-will.deacon@arm.com> References: <1515432758-26440-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marc Zyngier We will soon need to invoke a CPU-specific function pointer after changing page tables, so move post_ttbr_update_workaround out into C code to make this possible. Signed-off-by: Marc Zyngier Signed-off-by: Will Deacon --- arch/arm64/include/asm/assembler.h | 13 ------------- arch/arm64/kernel/entry.S | 2 +- arch/arm64/mm/context.c | 9 +++++++++ arch/arm64/mm/proc.S | 3 +-- 4 files changed, 11 insertions(+), 16 deletions(-) -- 2.1.4 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index c45bc94f15d0..cee60ce0da52 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -476,17 +476,4 @@ alternative_endif mrs \rd, sp_el0 .endm -/* - * Errata workaround post TTBRx_EL1 update. - */ - .macro post_ttbr_update_workaround -#ifdef CONFIG_CAVIUM_ERRATUM_27456 -alternative_if ARM64_WORKAROUND_CAVIUM_27456 - ic iallu - dsb nsh - isb -alternative_else_nop_endif -#endif - .endm - #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 6ceed4877daf..80b539845da6 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -277,7 +277,7 @@ alternative_else_nop_endif * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache * corruption). */ - post_ttbr_update_workaround + bl post_ttbr_update_workaround .endif 1: .if \el != 0 diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 1cb3bc92ae5c..5f7097d0cd12 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -239,6 +239,15 @@ void check_and_switch_context(struct mm_struct *mm, unsigned int cpu) cpu_switch_mm(mm->pgd, mm); } +/* Errata workaround post TTBRx_EL1 update. */ +asmlinkage void post_ttbr_update_workaround(void) +{ + asm(ALTERNATIVE("nop; nop; nop", + "ic iallu; dsb nsh; isb", + ARM64_WORKAROUND_CAVIUM_27456, + CONFIG_CAVIUM_ERRATUM_27456)); +} + static int asids_init(void) { asid_bits = get_cpu_asid_bits(); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 3146dc96f05b..6affb68a9a14 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -145,8 +145,7 @@ ENTRY(cpu_do_switch_mm) isb msr ttbr0_el1, x0 // now update TTBR0 isb - post_ttbr_update_workaround - ret + b post_ttbr_update_workaround // Back to C code... ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "ax"