From patchwork Tue Feb 6 17:45:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 127044 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp3096380ljc; Tue, 6 Feb 2018 09:00:15 -0800 (PST) X-Google-Smtp-Source: AH8x225EvT0ga/zCXbt4Q+mQ3OF7RlUh5+884hxVFNnlitcXOjBdCc7mCnP/NjVsAnMER9jWg1x8 X-Received: by 2002:a17:902:8607:: with SMTP id f7-v6mr3033321plo.273.1517936415724; Tue, 06 Feb 2018 09:00:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517936415; cv=none; d=google.com; s=arc-20160816; b=IV7Apeyl+2ywaWPU4OvvvFHHoQglvX+0ZjobYBGqKCeZogxjIA+rxT/xrLvOqUyIhE 6Xr0xZx8ApTicQ1umsTsCxaSf/DoH8c4MQ9NYI6m54zZXC8XmXb6rLfqXx1ew950Em2+ PdjjU18EkzDO6P9Caz3ZMQDKIZcoHDXd6J+ovN7nnkeNdwTvAER7nlHevyFJz6nWjfKa 188RcKJO9nkFB31Fb/skPxtfHAdgO1nMSc5ZIVAw7llqsH8IQ/EgQX/EC918IwkWfUyI KDR9dnqfuZ8O6bRwU6UdRLWarHPC6Ck5sx0S94yQvDl80XYIB90JwAD0p2bQTMa+o0db V4YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=sN3eqotvkEgMwhkjT4vk60Y69jDi0v8CALAdkjjZJSE=; b=SGaPAV0sHuv58lscG03FwBbHQAFJVuMob6MQLVzqjgIthSUo6ANAGZ/Vzi4twbt/sm /7043A/zqVp88I9ROzZxsBmUCDcvYy/vUt2O4jQ2gvgDtt7yJDnYRoVBtZSJll1MyxL9 qkMbkfo8VHEIA/73uBy+UBSwZYrg8RAepflZIscJ4YCjxR5LyDXNYHJ8rEM6E/anPDbF smyTOTxrPFudBsFACF2eBcc44/mtLumHFoReREHhH1KfiyMH7hp6TqhbwzAKsk+Cwm60 4CCzuIQoTXgcbWWihl90/BTb/TbBQZkjVrf77sbHp38WH7wINGaJpOljrb0znteTUvqB p0Dw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s13-v6si9013984plq.557.2018.02.06.09.00.15; Tue, 06 Feb 2018 09:00:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753226AbeBFRAN (ORCPT + 21 others); Tue, 6 Feb 2018 12:00:13 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:51743 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1752927AbeBFQ4J (ORCPT ); Tue, 6 Feb 2018 11:56:09 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id BD8BFDC9D9354; Wed, 7 Feb 2018 00:55:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.361.1; Wed, 7 Feb 2018 00:55:52 +0800 From: John Garry To: , , , , , , , , , CC: , , , , "John Garry" Subject: [PATCH 7/9] perf utils: fixup Cavium ThunderX2 JSON to use ARMv8 recommended events Date: Wed, 7 Feb 2018 01:45:02 +0800 Message-ID: <1517939104-230881-8-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517939104-230881-1-git-send-email-john.garry@huawei.com> References: <1517939104-230881-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch fixes the Cavium ThunderX2 JSON to use event definitions from the ARMv8 recommended events. The brief description is kept for readability for arch standard events, but is not strictly required. Signed-off-by: John Garry --- .../arch/arm64/cavium/thunderx2/core-imp-def.json | 60 ++++++++-------------- 1 file changed, 20 insertions(+), 40 deletions(-) -- 1.9.1 diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json index 2db45c4..f47bf0f 100644 --- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json @@ -1,62 +1,42 @@ [ { - "PublicDescription": "Attributable Level 1 data cache access, read", - "EventCode": "0x40", - "EventName": "l1d_cache_rd", - "BriefDescription": "L1D cache read", + "ArchStdEvent": "0x40", + "BriefDescription": "L1D cache access, read" }, { - "PublicDescription": "Attributable Level 1 data cache access, write ", - "EventCode": "0x41", - "EventName": "l1d_cache_wr", - "BriefDescription": "L1D cache write", + "ArchStdEvent": "0x41", + "BriefDescription": "L1D cache access, write" }, { - "PublicDescription": "Attributable Level 1 data cache refill, read", - "EventCode": "0x42", - "EventName": "l1d_cache_refill_rd", - "BriefDescription": "L1D cache refill read", + "ArchStdEvent": "0x42", + "BriefDescription": "L1D cache refill, read" }, { - "PublicDescription": "Attributable Level 1 data cache refill, write", - "EventCode": "0x43", - "EventName": "l1d_cache_refill_wr", - "BriefDescription": "L1D refill write", + "ArchStdEvent": "0x43", + "BriefDescription": "L1D cache refill, write" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, read", - "EventCode": "0x4C", - "EventName": "l1d_tlb_refill_rd", - "BriefDescription": "L1D tlb refill read", + "ArchStdEvent": "0x4C", + "BriefDescription": "L1D cache refill, inner" }, { - "PublicDescription": "Attributable Level 1 data TLB refill, write", - "EventCode": "0x4D", - "EventName": "l1d_tlb_refill_wr", - "BriefDescription": "L1D tlb refill write", + "ArchStdEvent": "0x4D", + "BriefDescription": "L1D tlb refill, write" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, read", - "EventCode": "0x4E", - "EventName": "l1d_tlb_rd", - "BriefDescription": "L1D tlb read", + "ArchStdEvent": "0x4E", + "BriefDescription": "L1D tlb access, read" }, { - "PublicDescription": "Attributable Level 1 data or unified TLB access, write", - "EventCode": "0x4F", - "EventName": "l1d_tlb_wr", - "BriefDescription": "L1D tlb write", + "ArchStdEvent": "0x4F", + "BriefDescription": "L1D tlb access, write" }, { - "PublicDescription": "Bus access read", - "EventCode": "0x60", - "EventName": "bus_access_rd", - "BriefDescription": "Bus access read", + "ArchStdEvent": "0x60", + "BriefDescription": "Bus access read" }, { - "PublicDescription": "Bus access write", - "EventCode": "0x61", - "EventName": "bus_access_wr", - "BriefDescription": "Bus access write", + "ArchStdEvent": "0x61", + "BriefDescription": "Bus access write" } ]