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[v2,09/11] perf vendor events arm64: fixup ThunderX2 to use recommended events

Message ID 1519401932-205051-10-git-send-email-john.garry@huawei.com
State New
Headers show
Series perf events patches for improved ARM64 support | expand

Commit Message

John Garry Feb. 23, 2018, 4:05 p.m. UTC 
This patch fixes the Cavium ThunderX2 JSON to use event definitions
from the ARMv8 recommended events.

The brief description is kept for readability, but is not strictly
required.

Cc: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
Signed-off-by: John Garry <john.garry@huawei.com>

---
 .../arch/arm64/cavium/thunderx2/core-imp-def.json  | 60 ++++++++--------------
 1 file changed, 20 insertions(+), 40 deletions(-)

-- 
1.9.1
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Patch

diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
index 2db45c4..f47bf0f 100644
--- a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
+++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2/core-imp-def.json
@@ -1,62 +1,42 @@ 
 [
     {
-        "PublicDescription": "Attributable Level 1 data cache access, read",
-        "EventCode": "0x40",
-        "EventName": "l1d_cache_rd",
-        "BriefDescription": "L1D cache read",
+        "ArchStdEvent": "0x40",
+        "BriefDescription": "L1D cache access, read"
     },
     {
-        "PublicDescription": "Attributable Level 1 data cache access, write ",
-        "EventCode": "0x41",
-        "EventName": "l1d_cache_wr",
-        "BriefDescription": "L1D cache write",
+        "ArchStdEvent": "0x41",
+        "BriefDescription": "L1D cache access, write"
     },
     {
-        "PublicDescription": "Attributable Level 1 data cache refill, read",
-        "EventCode": "0x42",
-        "EventName": "l1d_cache_refill_rd",
-        "BriefDescription": "L1D cache refill read",
+        "ArchStdEvent": "0x42",
+        "BriefDescription": "L1D cache refill, read"
     },
     {
-        "PublicDescription": "Attributable Level 1 data cache refill, write",
-        "EventCode": "0x43",
-        "EventName": "l1d_cache_refill_wr",
-        "BriefDescription": "L1D refill write",
+        "ArchStdEvent": "0x43",
+        "BriefDescription": "L1D cache refill, write"
     },
     {
-        "PublicDescription": "Attributable Level 1 data TLB refill, read",
-        "EventCode": "0x4C",
-        "EventName": "l1d_tlb_refill_rd",
-        "BriefDescription": "L1D tlb refill read",
+        "ArchStdEvent": "0x4C",
+        "BriefDescription": "L1D cache refill, inner"
     },
     {
-        "PublicDescription": "Attributable Level 1 data TLB refill, write",
-        "EventCode": "0x4D",
-        "EventName": "l1d_tlb_refill_wr",
-        "BriefDescription": "L1D tlb refill write",
+        "ArchStdEvent": "0x4D",
+        "BriefDescription": "L1D tlb refill, write"
     },
     {
-        "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
-        "EventCode": "0x4E",
-        "EventName": "l1d_tlb_rd",
-        "BriefDescription": "L1D tlb read",
+        "ArchStdEvent": "0x4E",
+        "BriefDescription": "L1D tlb access, read"
     },
     {
-        "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
-        "EventCode": "0x4F",
-        "EventName": "l1d_tlb_wr",
-        "BriefDescription": "L1D tlb write",
+        "ArchStdEvent": "0x4F",
+        "BriefDescription": "L1D tlb access, write"
     },
     {
-        "PublicDescription": "Bus access read",
-        "EventCode": "0x60",
-        "EventName": "bus_access_rd",
-        "BriefDescription": "Bus access read",
+        "ArchStdEvent": "0x60",
+        "BriefDescription": "Bus access read"
    },
    {
-        "PublicDescription": "Bus access write",
-        "EventCode": "0x61",
-        "EventName": "bus_access_wr",
-        "BriefDescription": "Bus access write",
+        "ArchStdEvent": "0x61",
+        "BriefDescription": "Bus access write"
    }
 ]