From patchwork Thu Mar 1 07:22:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 130117 Delivered-To: patch@linaro.org Received: by 10.80.172.228 with SMTP id x91csp2472487edc; Wed, 28 Feb 2018 23:23:00 -0800 (PST) X-Google-Smtp-Source: AG47ELv3aW8Ri7L1Z6joQ/uUsRfIvEUzDZ8cjF0cII06B9lnswDMELjYo44UNbiLjh7dRxTtVBN0 X-Received: by 10.98.138.217 with SMTP id o86mr978846pfk.128.1519888980701; Wed, 28 Feb 2018 23:23:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1519888980; cv=none; d=google.com; s=arc-20160816; b=n1QKIup6BzW/N+1ETeX5UrpLzZ+BHAPeK+sxToLtElnz0HSdVaOef62v66uIiW+Xz/ O/KsnbVLk3Cj02+aH3PFbK+8WzGrYni0AoR8FJ1FWMI+CfVhKsyVLCY+Tb9ARWT/JHVG 6ikO7Qc4boeY2OvS12rPQVslpYlYUqUwnRdCzWt5PzmlNdGPIv1Ifj34mpB6stzJ+miW o24sCczOvUBAHUWrdB89AcKc9j479g2ZnEqj45mDOZOQt4k0QeUy/dN8rLv0UVsWsVOG voq9fVUAuXxHC0FoKIWm9Zkky5mgWV7vmUM3EztZ05ButCQhzR4IhHrOvbQuX6CrHJ63 amNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=c8YxUW3/WKeOxi9JK6sz6PB5cFt8r/+GZyR9ZJYXAVE=; b=AxIGey/uRG0cMPWQAdE9A/MGgMwULJptfl79esoGemIiDF1H/cMnloOqeVBkRCUIjg VbD9N66Y1l0r3KTPstNX4al+iWuytYYHRGN8BYXygeCiJiq0c7am3NCF1+uXK7eTlinA IXoVYHndXgnW2Qu0iQCF7pprVf1l++40IfMlW7/KU6fBMnEO4qy9P1oYjJ7kqoKI90CV pcSixEA7ubk+kjaT5WMLKh/fzfzMckQ++8PU7rN4ex04CmraW1y+HujjWLm1Oum/dX5R UFc7HF9L2M9+f6yAEcSyhrtKvk6z6Zn61ja3CUbKZ8SVAChqH1IPwBhY6pgdIdxmuH5r C9Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=de1aqMjN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 34-v6si943023plz.589.2018.02.28.23.23.00; Wed, 28 Feb 2018 23:23:00 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=de1aqMjN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S966495AbeCAHW5 (ORCPT + 28 others); Thu, 1 Mar 2018 02:22:57 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:43838 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966417AbeCAHWx (ORCPT ); Thu, 1 Mar 2018 02:22:53 -0500 Received: by mail-pf0-f193.google.com with SMTP id z14so2101745pfe.10 for ; Wed, 28 Feb 2018 23:22:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=c8YxUW3/WKeOxi9JK6sz6PB5cFt8r/+GZyR9ZJYXAVE=; b=de1aqMjN39IEClHBi0FFjogN/4Ppf8eIQfsVCX4wEAOCAU+8PKmz+VhKJ9QOuCxDoT i3abyuRB4kNeeg0IhqKNWifIywzYg65+y63SM59Jni+TqdDMB6pSb6bsZWm88ekf9ClC WpqAOjfKbuvPP0YtITeiULWBynPKKuMF2pjqg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c8YxUW3/WKeOxi9JK6sz6PB5cFt8r/+GZyR9ZJYXAVE=; b=cKM+N8TFwZQHoHC/HKme9AgDh68QihqEDFBlpyaEI3RXGLDlnWKqaFcPSns/GxjS9I iYs4XfNkeaaXVtQY4vH9o25mhLqNn+mptlHaIVUEzwtjf5kL37GogaPUB73+rdeGkcL1 A2eGJRxy6LvbnUVpQPXP73WaX3EXHOprJRR/EWTA63jYSVQxbOxWQQDdy4szXLk1bcyR b+dUUAGQ34ECcVm0yAU/Rcs4bKNw874lB5K6XucH/W07NqsL3spfRJTqgmsXRSALIynY 2BVU7BrnhBcHcpzSK+YcLvnuEypWO7mNtyBqtKpoGH7GreerUGfGVlJ+MqFjzT+GEeIl OIoQ== X-Gm-Message-State: APf1xPAIza/7R1kkhrltLPZMj55hcPKchX2av5jOvpagDfcujz/unzPx os0B340JgVcGyBfkdc7HQoccXw== X-Received: by 10.98.65.198 with SMTP id g67mr954404pfd.127.1519888972757; Wed, 28 Feb 2018 23:22:52 -0800 (PST) Received: from localhost.localdomain ([104.237.91.69]) by smtp.gmail.com with ESMTPSA id u21sm2440394pfg.60.2018.02.28.23.22.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Feb 2018 23:22:51 -0800 (PST) From: Shawn Guo To: Kishon Vijay Abraham I Cc: Rob Herring , Jianguo Sun , Jiancheng Xue , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengcheng Li , Shawn Guo Subject: [PATCH v3 1/2] dt-bindings: add bindings doc for HiSilicon INNO USB2 PHY Date: Thu, 1 Mar 2018 15:22:19 +0800 Message-Id: <1519888940-23235-2-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1519888940-23235-1-git-send-email-shawn.guo@linaro.org> References: <1519888940-23235-1-git-send-email-shawn.guo@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Pengcheng Li It adds device tree bindings document for HiSilicon INNO USB2 PHY. Signed-off-by: Pengcheng Li Signed-off-by: Jiancheng Xue Signed-off-by: Shawn Guo --- .../devicetree/bindings/phy/phy-hisi-inno-usb2.txt | 52 ++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt new file mode 100644 index 000000000000..b563cf54ca7b --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-hisi-inno-usb2.txt @@ -0,0 +1,52 @@ +HiSilicon INNO USB2 PHY + +Required properties: +- compatible: Should be one of the following strings: + "hisilicon,inno-usb2-phy", + "hisilicon,hi3798cv200-usb2-phy". +- reg: Should be the address space for PHY configuration register in peripheral + controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798cv200 SoC. +- #phy-cells: Should be 1. The specifier is the index of the PHY port to + reference. +- clocks: The phandle and clock specifier pair for reference clock utmi_refclk. +- resets: The list of phandle and reset specifier pairs for each reset signal + in reset-names. +- reset-names: Should contain "power_on", "utmi0" and "utmi1". The "utmi1" + should exist only if the device has two PHY port. + +Refer to phy/phy-bindings.txt for the generic PHY binding properties + +Note: the device node should be a child of peripheral controller that contains +the PHY configuration register. + +Example: + +perictrl: peripheral-controller@8a20000 { + compatible = "hisilicon,hi3798cv200-perictrl", "syscon", + "simple-mfd"; + reg = <0x8a20000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x8a20000 0x1000>; + + usb2_phy1: phy@120 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x120 0x4>; + #phy-cells = <1>; + clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; + resets = <&crg 0xbc 4>, + <&crg 0xbc 8>, + <&crg 0xbc 9>; + reset-names = "power_on", "utmi0", "utmi1"; + }; + + usb2_phy2: phy@124 { + compatible = "hisilicon,hi3798cv200-usb2-phy"; + reg = <0x124 0x4>; + #phy-cells = <1>; + clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; + resets = <&crg 0xbc 6>, + <&crg 0xbc 10>; + reset-names = "power_on", "utmi0"; + }; +};