From patchwork Fri Mar 30 09:44:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 132593 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp2828003ljb; Fri, 30 Mar 2018 02:44:32 -0700 (PDT) X-Google-Smtp-Source: AIpwx49eOqzYndN3Zj4TScTIU+2t5x/1pZGcNij+nUtrXNQYACzGL574BrinMGRMLwtOlEDEjn1j X-Received: by 10.98.180.24 with SMTP id h24mr9318555pfn.213.1522403072053; Fri, 30 Mar 2018 02:44:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1522403072; cv=none; d=google.com; s=arc-20160816; b=UCBJ3rzP2ityglZGPEmUCDkwTIizd/vtg3dNYoBUEneXHvbHcU5MkC3BraNMemZ9PT m/VagVBdJZmzIlC9JL/1dYjiew4MuQagcDv2DbbbuDVoYcw0iYk3BSFERHHRHJSp8Jdf SmaN3QIVSry/qPB1/UrRnKt2nyiLe9C/r7jkIoffoAAiodt5g6eGryc1eeDIqoR6jc52 e83UVGPgmo2vXwDmz/YvMhxJvuPhjq4sNj8k5e68IXnFCLlKidSGMfe1MkwqJUwkz5Uz zPL94tVRwpu+62L1sTB3Ev1WUIA8pt/DyPFm0mS0brx7zgSzOTLQ5r3+pwX3H+Bd57to xU6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=CjJMtzTS+ufS8WlJGGf9iJkWVFOwKBVKJdHi/vrTBmo=; b=bI6Yo269mCl7kbkxxBDSak3cHl/kQR1w8bhv8vUZOAGmI6XIpY4paBEkNnzPeWma2H /60wI9GE2K7CH91sP0MP521GeqcP6q37Qs7U0QWAZjhkY4+m5GQaNbEIxU3lw8YmiSsj LoYvq0ym1y5nbFoc9sYm+YZTv9aLVzpO+OZX4bLbNMm0QtOBm/NY1r5o2T09vtV/4k/1 orIExGsqT6gw6qt4geLY48FWMe0RFFoSCeegh/MKvYhfGMbsgHu0a17G9hmUCUe3Hc6D tGamaBEu0yHsFrDAeEsmiDZCRz30INpwH3X5QQGilaf+FEnTTsPdg1fEr1+WZdLuPNLM Lecw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f12-v6si8683455pln.211.2018.03.30.02.44.31; Fri, 30 Mar 2018 02:44:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751403AbeC3Jo2 (ORCPT + 29 others); Fri, 30 Mar 2018 05:44:28 -0400 Received: from mx.socionext.com ([202.248.49.38]:52266 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751237AbeC3JoY (ORCPT ); Fri, 30 Mar 2018 05:44:24 -0400 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 30 Mar 2018 18:44:23 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 7E9B6180CA5; Fri, 30 Mar 2018 18:44:23 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 30 Mar 2018 18:44:23 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 27C1A1A0DEC; Fri, 30 Mar 2018 18:44:23 +0900 (JST) From: Kunihiko Hayashi To: Michael Turquette , Stephen Boyd , Masahiro Yamada , linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kunihiko Hayashi Subject: [PATCH 3/3] clk: uniphier: add additional ethernet clock lines for Pro4 Date: Fri, 30 Mar 2018 18:44:14 +0900 Message-Id: <1522403054-18691-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1522403054-18691-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1522403054-18691-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Pro4 SoC has clock lines for Giga-bit feature and ethernet phy, and these are mandatory to activate the ethernet controller. This adds support for the clock lines. Signed-off-by: Kunihiko Hayashi --- drivers/clk/uniphier/clk-uniphier-sys.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.7.4 Acked-by: Masahiro Yamada diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c index 7d66dfb..ebc78ab2 100644 --- a/drivers/clk/uniphier/clk-uniphier-sys.c +++ b/drivers/clk/uniphier/clk-uniphier-sys.c @@ -102,13 +102,16 @@ const struct uniphier_clk_data uniphier_pro4_sys_clk_data[] = { UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */ UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */ UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */ + UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */ UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8), UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32), UNIPHIER_LD4_SYS_CLK_NAND(2), UNIPHIER_LD4_SYS_CLK_SD, UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12), UNIPHIER_PRO4_SYS_CLK_ETHER(6), + UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5), UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */ + UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0), UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */ UNIPHIER_PRO4_SYS_CLK_USB3(14, 0), UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),