From patchwork Wed Apr 11 18:01:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 133168 Delivered-To: patch@linaro.org Received: by 10.46.84.29 with SMTP id i29csp897769ljb; Wed, 11 Apr 2018 11:03:58 -0700 (PDT) X-Google-Smtp-Source: AIpwx4/KLZm/MgtgT5iWFsbs/WGGlSaN0+STag0YunvP+2KAB2jRz66nn/Bd/AQUM12TL4Z5ssmH X-Received: by 2002:a17:902:7e42:: with SMTP id a2-v6mr6137535pln.13.1523469838774; Wed, 11 Apr 2018 11:03:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1523469838; cv=none; d=google.com; s=arc-20160816; b=NpOxlM8YiQka/SgVtlo4iInFf+Z/45kre4li4/jeabd3NvwrXrAUNgj1KkZLr1wjSi CiZ+SzPLI0vglvpdGDLa6cNqwu6oEbH/JYVvYLFmKHt6jP33nMiu/qAVExkU0dcZy+P+ BWT1UJW77Pkw0e/yC1W6wpcOzrVZ4Z9TCh37AXeS6kAmJal26ikrlxTYzqwkziISqcl9 ddm16CENfVAlvWywgIT/nbqewpq7hR/8wUCLGyhc+tgouPQ2ASo24n3S14dB5t+BDeDR R2+4Ja3Rwa83aWbwq1a++oXzT0CxYPhMavSOUa/RctGZQTLz1AdP41GPRRvPF7rW4MUs LfEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Gd79BK1RjZEjjy2T6jUzYMNwBJjAvxevnUzM+pM9VQo=; b=weYMuXWVPw9NpvlJ4px6E2uwMxiEK4EITYOscjFdPlePn2B9/OcRPipI0gXlzzcdnG 3KO/f3XorXSJYXfFUyVQUTkiuC/INZ96pq9zcC0bTZbysMm3SvpqXgM5mBxdBCuMGO07 cLXdg+8GYuYAbTTXloFuM8Tl0aGqYfDGgXvToeaxtfVHDYWKdamPW/JCrYgaQIWVEnVA KtKKZfvfYpgdS70jI6iKcsuA4ayl/YX6JbQ++3LL8CURVeBlSkvbAbUNmBQZq0Mf8eIQ 0eBqnQ8MZc1yo6Du9hmNJd1BHK/VpPp9LO8ruAb4mB01GPPBAEnVho+aNMAKYAaDdON0 ry+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g5si1074288pgr.411.2018.04.11.11.03.58; Wed, 11 Apr 2018 11:03:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754075AbeDKSCy (ORCPT + 29 others); Wed, 11 Apr 2018 14:02:54 -0400 Received: from foss.arm.com ([217.140.101.70]:52156 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752669AbeDKSBH (ORCPT ); Wed, 11 Apr 2018 14:01:07 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4E33416EA; Wed, 11 Apr 2018 11:01:07 -0700 (PDT) Received: from edgewater-inn.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1EB353F614; Wed, 11 Apr 2018 11:01:07 -0700 (PDT) Received: by edgewater-inn.cambridge.arm.com (Postfix, from userid 1000) id 1202B1AE55D9; Wed, 11 Apr 2018 19:01:22 +0100 (BST) From: Will Deacon To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, peterz@infradead.org, mingo@kernel.org, boqun.feng@gmail.com, paulmck@linux.vnet.ibm.com, longman@redhat.com, Will Deacon Subject: [PATCH v2 12/13] locking/qspinlock: Use try_cmpxchg instead of cmpxchg when locking Date: Wed, 11 Apr 2018 19:01:19 +0100 Message-Id: <1523469680-17699-13-git-send-email-will.deacon@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1523469680-17699-1-git-send-email-will.deacon@arm.com> References: <1523469680-17699-1-git-send-email-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When reaching the head of an uncontended queue on the qspinlock slow-path, using a try_cmpxchg instead of a cmpxchg operation to transition the lock work to _Q_LOCKED_VAL generates slightly better code for x86 and pretty much identical code for arm64. Cc: Ingo Molnar Reported-by: Peter Zijlstra Signed-off-by: Will Deacon --- kernel/locking/qspinlock.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) -- 2.1.4 diff --git a/kernel/locking/qspinlock.c b/kernel/locking/qspinlock.c index fa5d2ab369f9..1e3ddc42135e 100644 --- a/kernel/locking/qspinlock.c +++ b/kernel/locking/qspinlock.c @@ -467,16 +467,15 @@ void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val) * Otherwise, we only need to grab the lock. */ - /* In the PV case we might already have _Q_LOCKED_VAL set */ - if ((val & _Q_TAIL_MASK) == tail) { - /* - * The atomic_cond_read_acquire() call above has provided the - * necessary acquire semantics required for locking. - */ - old = atomic_cmpxchg_relaxed(&lock->val, val, _Q_LOCKED_VAL); - if (old == val) - goto release; /* No contention */ - } + /* + * In the PV case we might already have _Q_LOCKED_VAL set. + * + * The atomic_cond_read_acquire() call above has provided the + * necessary acquire semantics required for locking. + */ + if (((val & _Q_TAIL_MASK) == tail) && + atomic_try_cmpxchg_relaxed(&lock->val, &val, _Q_LOCKED_VAL)) + goto release; /* No contention */ /* Either somebody is queued behind us or _Q_PENDING_VAL is set */ set_locked(lock);