From patchwork Wed May 2 15:56:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 134843 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp846828lji; Wed, 2 May 2018 08:58:11 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoAwfZMYuCmxJJdrV3ZXSg13s2P+vfp58tv6rnpK5mZtSydxQLpRW1dc/hQ/ZFbJjL2Luqw X-Received: by 10.98.137.219 with SMTP id n88mr19731407pfk.11.1525276691338; Wed, 02 May 2018 08:58:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525276691; cv=none; d=google.com; s=arc-20160816; b=i6fxH6YgA4J8b1Iym4nKudmr49kqGGW/yBnoTGiLGpXBdd5+MHIuEIOglzHA96M3g6 MPsi04DyV0SNReEKRCTZWPtb2eUHnQK6uYAVuqu8WLpujdwKhiiricIX7G/5tdwNJ+1Y 8UWKUzZNRuZCaHGoAsijEWY8eiYQwFV8wTVkMoZyFRmjNEzDXlbjXSpB+U3R/ZfW+GF6 LIMvUIlRxGrBksCksh+dtMQFDF+W5d/GlnrEK5k5sSKuuWwEWEStC93I4BcEZC9KSCu/ UguZhRMj9jx201uYAMDvIxijR08jqE6UM9ucT5ml4IDjrCbVWycihFzLlGkwVHmiY1He WbCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=RQpl3Th6+siYmVJaqwb6UjublRx03pKHi8ZQwBOzH9k=; b=RrwuGUb4m4T+2Ma/reJ4Jyp2Y7Ms8ejSArcJ1BYOKLfQcqiRnEHJndloPyg9n62KEp MmHgRSAuydaoXeUOE833gBsfPh1lrbtxdjw+L1NOv2aBDGE7vnMimjs3OJ8X5m15zX27 ts9cJsl2+Kk0OxrdchbpjIkqNqMP73MicjiZRvPqsMu15GdJf4W/N7yXeikJ4x/honij sUCFpYKbCUtZ4XaRkG1Z8YfOkoLiPHZxqU6JBcz9AfOJe8zxXW1L4FDBMFlUceWVPfa5 BOJIXpNm4ERf5TWBVz5XvsJRoxzpSGAI25qfhpMeDYlCbTBkhwd4bIuwIselP9MH97+M plRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4-v6si9494358pgv.681.2018.05.02.08.58.11; Wed, 02 May 2018 08:58:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752121AbeEBP6I (ORCPT + 29 others); Wed, 2 May 2018 11:58:08 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:7220 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752044AbeEBP5o (ORCPT ); Wed, 2 May 2018 11:57:44 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 081F9A85C3521; Wed, 2 May 2018 23:57:27 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.361.1; Wed, 2 May 2018 23:57:19 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 11/11] scsi: hisi_sas: workaround a v3 hw hilink bug Date: Wed, 2 May 2018 23:56:34 +0800 Message-ID: <1525276594-92173-12-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1525276594-92173-1-git-send-email-john.garry@huawei.com> References: <1525276594-92173-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan There is an SoC bug of v3 hw development version. When hot- unplugging a directly attached disk, the PHY down interrupt may not happen. It is very easy to appear on some boards. When this issue occurs, the controller will receive many invalid dword frames, and the "alos" fields of register HILINK_ERR_DFX can indicate that disk was unplugged. As an workaround solution, this patch detects this issue in the channel interrupt, and workaround it by following steps: - Disable the PHY - Clear error code and interrupt - Enable the PHY Then the HW will reissue PHY down interrupt. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 28bb71e..492c3be 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -106,6 +106,7 @@ #define COMPL_Q_0_RD_PTR 0x4f0 #define AWQOS_AWCACHE_CFG 0xc84 #define ARQOS_ARCACHE_CFG 0xc88 +#define HILINK_ERR_DFX 0xe04 /* phy registers requiring init */ #define PORT_BASE (0x2000) @@ -167,6 +168,7 @@ #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 #define CHL_INT2 (PORT_BASE + 0x1bc) #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 +#define CHL_INT2_RX_INVLD_DW_OFF 30 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) #define CHL_INT1_MSK (PORT_BASE + 0x1c4) @@ -1345,6 +1347,7 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) { struct hisi_hba *hisi_hba = p; struct device *dev = hisi_hba->dev; + struct pci_dev *pci_dev = hisi_hba->pci_dev; u32 irq_msk; int phy_no = 0; @@ -1410,8 +1413,28 @@ static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value2); - } + if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && + (pci_dev->revision == 0x20)) { + u32 reg_value; + int rc; + + rc = hisi_sas_read32_poll_timeout_atomic( + HILINK_ERR_DFX, reg_value, + !((reg_value >> 8) & BIT(phy_no)), + 1000, 10000); + if (rc) { + disable_phy_v3_hw(hisi_hba, phy_no); + hisi_sas_phy_write32(hisi_hba, phy_no, + CHL_INT2, + BIT(CHL_INT2_RX_INVLD_DW_OFF)); + hisi_sas_phy_read32(hisi_hba, phy_no, + ERR_CNT_INVLD_DW); + mdelay(1); + enable_phy_v3_hw(hisi_hba, phy_no); + } + } + } if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { hisi_sas_phy_write32(hisi_hba, phy_no,