From patchwork Mon May 21 10:09:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 136446 Delivered-To: patch@linaro.org Received: by 2002:a2e:9706:0:0:0:0:0 with SMTP id r6-v6csp121428lji; Mon, 21 May 2018 03:14:04 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoTex/8+p0C3AfwkdEYqTb1RkhTtetCfdUCxTztUIhRi1o/Gp8wogo5L3OamMoRDY1bm/Cx X-Received: by 2002:a17:902:680c:: with SMTP id h12-v6mr20254038plk.113.1526897644780; Mon, 21 May 2018 03:14:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1526897644; cv=none; d=google.com; s=arc-20160816; b=dL6bzTQ8xxeq3HhA8dLvQGhIcHgJAqWrSFMuooxmvVdhTS0dCakI0A4ZZPEUlnbVDk dFyGtjWqtCgxDc4go0ZcGuN2DJvPjnqCjbzrQOw2j+LO4Wg/4cgYA+cg49HCyjxVyM9l n9gnkeji2kt9gqGAZUSkfWKpzrGonVIC1cHwZGUFfh5eoeZVhP+FBme08ahi1UnYN5b7 elGnnU+yq4O8HV6j2PZ+s7mhbq/oP/vRWCfjwo3i5Y77PpSBqSqXZ1Fv9LGg8w7VNjGx LnlUbZqtgaItPhNdkgDftumbup8/MWmuKSN27gRx3Y4rd3qluwWQSDiC0+hveAX6EUfg qZyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=uxv0sM1Uyh8C5Dj7awa9KZEzNngW4C6oZ1eVrClslJ8=; b=qySegj1z11ol0biAvluoliEeLsdzvMgwIvyGlUfPvBbVAUZvDy+xAm2F2DQWiu2XLm +pixzkxNu8zXsZ57Ts25WXdYQ328lcAHRrPp+o3WMl2HXuxy9Mz1g4pkmlCH9Cre0MwO HlSEJBu6uFFXhykG1dMgGPrJdzWbT0WKYR0iqUBRKLV3NTxbWaycWsLy4Zu1bnddeTOZ PYNq9jYqthMiQnpybvYhL4a9u60uSesLP406B8s2ca5jkxv3HVWnLG2Y3mUtl37uIqb+ VqqESOG0I5tchp8HkNgPxTbHqJY2+vZ+TolYgR6ecCjZIMQogh+bSxOLmspiPWnTFgg/ Ut5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c65-v6si14075311pfa.99.2018.05.21.03.14.04; Mon, 21 May 2018 03:14:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752633AbeEUKLm (ORCPT + 29 others); Mon, 21 May 2018 06:11:42 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:55739 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751202AbeEUKLj (ORCPT ); Mon, 21 May 2018 06:11:39 -0400 Received: from DGGEMS410-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 43D009D371F03; Mon, 21 May 2018 18:11:35 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS410-HUB.china.huawei.com (10.3.19.210) with Microsoft SMTP Server id 14.3.382.0; Mon, 21 May 2018 18:11:29 +0800 From: John Garry To: , CC: , , , Xiaofei Tan , "John Garry" Subject: [PATCH 04/13] scsi: hisi_sas: Add LED feature for v3 hw Date: Mon, 21 May 2018 18:09:16 +0800 Message-ID: <1526897365-228549-5-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526897365-228549-1-git-send-email-john.garry@huawei.com> References: <1526897365-228549-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Xiaofei Tan This patch implements LED feature of directly attached disk for v3 hw. In fact, this hw has created an SGPIO component for LED feature, and we can control LEDs just by internal registers. Signed-off-by: Xiaofei Tan Signed-off-by: John Garry --- drivers/scsi/hisi_sas/hisi_sas_v3_hw.c | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) -- 1.9.1 diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c index 0a80a39..a043d9c 100644 --- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c +++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c @@ -107,6 +107,10 @@ #define AWQOS_AWCACHE_CFG 0xc84 #define ARQOS_ARCACHE_CFG 0xc88 #define HILINK_ERR_DFX 0xe04 +#define SAS_GPIO_CFG_0 0x1000 +#define SAS_GPIO_CFG_1 0x1004 +#define SAS_GPIO_TX_0_1 0x1040 +#define SAS_CFG_DRIVE_VLD 0x1070 /* phy registers requiring init */ #define PORT_BASE (0x2000) @@ -549,6 +553,14 @@ static void init_reg_v3_hw(struct hisi_hba *hisi_hba) hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); + + /* LED registers init */ + hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); + hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); + hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); + /* Configure blink generator rate A to 1Hz and B to 4Hz */ + hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); + hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); } static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) @@ -1974,6 +1986,35 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) return hw_init_v3_hw(hisi_hba); } +static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, + u8 reg_index, u8 reg_count, u8 *write_data) +{ + struct device *dev = hisi_hba->dev; + u32 *data = (u32 *)write_data; + int i; + + switch (reg_type) { + case SAS_GPIO_REG_TX: + if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { + dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", + reg_index, reg_index + reg_count - 1); + return -EINVAL; + } + + for (i = 0; i < reg_count; i++) + hisi_sas_write32(hisi_hba, + SAS_GPIO_TX_0_1 + (reg_index + i) * 4, + data[i]); + break; + default: + dev_err(dev, "write gpio: unsupported or bad reg type %d\n", + reg_type); + return -EINVAL; + } + + return 0; +} + static const struct hisi_sas_hw hisi_sas_v3_hw = { .hw_init = hisi_sas_v3_init, .setup_itct = setup_itct_v3_hw, @@ -1999,6 +2040,7 @@ static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) .soft_reset = soft_reset_v3_hw, .get_phys_state = get_phys_state_v3_hw, .get_events = phy_get_events_v3_hw, + .write_gpio = write_gpio_v3_hw, }; static struct Scsi_Host *