From patchwork Tue Jul 10 01:14:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 141499 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3267310ljj; Mon, 9 Jul 2018 18:14:34 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe72SrbKhyGbPFAQJ6lb/UOXTD6lIyC9IaCmHw51eIijhzSiz1eUMPpBGSHslF9BfLqScxo X-Received: by 2002:a63:d80f:: with SMTP id b15-v6mr7218527pgh.347.1531185274119; Mon, 09 Jul 2018 18:14:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531185274; cv=none; d=google.com; s=arc-20160816; b=kgl0c4voHwfsdzBKx7jKB33vUzuF0pS37jau1aJ5es+6HnSg9cwdG/xj6jtdRsf5em MnGwT7iKCHnyizE1moFVZQYP82Re5KmHOvhqiukwl/zAVdf3q3zFdXlTvuensvnENf8S susHeDwnYqlQnLvdoAyl/socXUbeUKSUkRCBnsxbpwzSDn9I7b/yNIjb5ZLLvEo/4NUn JrWJI4wfR6Gr/oaKnV5f6PIUXCmYES6rToRFyw4ITDEozSuL57NU6j+MIqjwzzxECGbw zWvBIeccZPr69ldaVwXcpGU7Peqgl4fjY8SHhY8/8lAhk2UXQVI14PsW20ZLydfLfbBu /U9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=Q4ozquygVOi1wfiB+tdEG9CKf6KORn+86ximYKdAQ4Y=; b=ZRsxoKSKRT6T5L3jEc77DB5k735vwiIbHXl4yHUh8Iq0saD8VFf6wGDnlQTgFk7ue9 5hFQhS4RxubX+cnP7Ak38PI10p20cDZRl3Uyh7sQPl+qLbkowUWOY3q/Oej8zidAelBD JaZU9gAD0Np4wORfppuaT7I+q0yF7IC24Gn5ZyD/R5InmT7iu97MTHaSqM0h7UzkxZDS 0gkmkCYtUA8iD3w9VHLsB7VOxEg1ndfkDxrbZYXPjkeJU5ziTKD1Jh8KGyA3F0l2gtnq E69RNAgjfO6GFMyGW/OjdvfQQVYZcg7MQo7eQcmuABnWcCpDIN1H5Pz3UMIe12BJrBl/ EeqQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w185-v6si14490859pgb.599.2018.07.09.18.14.33; Mon, 09 Jul 2018 18:14:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754655AbeGJBO2 (ORCPT + 12 others); Mon, 9 Jul 2018 21:14:28 -0400 Received: from mx.socionext.com ([202.248.49.38]:55907 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754572AbeGJBOZ (ORCPT ); Mon, 9 Jul 2018 21:14:25 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 10 Jul 2018 10:14:24 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 1B94D60034; Tue, 10 Jul 2018 10:14:24 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 10 Jul 2018 10:14:24 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 4C85D1A11BB; Tue, 10 Jul 2018 10:14:23 +0900 (JST) From: Kunihiko Hayashi To: Philipp Zabel , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 1/2] dt-bindings: reset: uniphier: add USB3 core reset support Date: Tue, 10 Jul 2018 10:14:16 +0900 Message-Id: <1531185257-16444-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1531185257-16444-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for reset control of USB3 core implemented in UniPhier SoCs. The reset control belongs to USB3 glue layer. Signed-off-by: Kunihiko Hayashi --- .../devicetree/bindings/reset/uniphier-reset.txt | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) -- 2.7.4 diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt index 93efed6..101743d 100644 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ b/Documentation/devicetree/bindings/reset/uniphier-reset.txt @@ -118,3 +118,59 @@ Example: other nodes ... }; + + +USB3 core reset +--------------- + +USB3 core reset belongs to USB3 glue layer. Before using the core reset, +it is necessary to control the clocks and resets to enable this layer. +These clocks and resets should be described in each property. + +Required properties: +- compatible: Should be + "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC +- #reset-cells: Should be 1. +- reg: Specifies offset and length of the register set for the device. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + regulator { + ... + }; + + phy { + ... + }; + ... + };