From patchwork Tue Jul 10 01:27:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 141502 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp3276241ljj; Mon, 9 Jul 2018 18:27:33 -0700 (PDT) X-Google-Smtp-Source: AAOMgpe9iCHykntCxJi+ZFiSlD29plTY/ONZEmbYas+vfmNXKhmsCh/E/Wfyk/oMmral63kVZ+tK X-Received: by 2002:a62:401:: with SMTP id 1-v6mr5266012pfe.28.1531186053774; Mon, 09 Jul 2018 18:27:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531186053; cv=none; d=google.com; s=arc-20160816; b=hJM0gvFjyXntLIvNKS9zYhkUrtpU77g1C+k96am3GmYJjXVVZy4SxrJc6DenYd6lnr c+zPwZ3KwA2LbG9pI8Al7e9KzGLsgVXC+2CSisH1Zc4x7ZFYt0M88AInB0s3M9w4VKbA WV2TU+qqH25FaBH6M6iRItmt35+PQawIz0pBix2BkXWC5sBK5qIiNWvIBARiRYgMk6Pm VGQwaK7rXjMXwb8BeVUvOsg/C8YGd+ylvM5eZb1p1mxZJz3Pq4DntXVfdpe3YkwDjSzL lVzMluhOrBZgkSNbrx821oCiE+8FKehlLMlzOOoKbFNlnMRcZccHVKpPJGyUOiWT3Pth DmgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:arc-authentication-results; bh=nIftcubZsw2EFvKnb0o0/qbrxFchQNeqOm/M1dmX4DQ=; b=bEkWP+JjhbZhdgcsF/AE9it6vCV0YG2o6/DDAEZ2ABkC3SC1D+9Mv+INXnWIPQOgY8 wkhLgDWA2dBsf6x0QnodOdiateF7UxaxUHCDKdhLB3T0fh4/j0HsWPmBOTDLHSgO6H0n Tz4BM0ju+/9FhyJwG1mrHDwUANJvHM6vWlWBvH5j2sZ/zHmNtJJs+5EZfTiezF3Qy3X5 DyOemeBhNZ64sZ6XultIQ0O+Z2NAbgyIzWmQMzJl60vwbj4NXcQvMUpvFx1BuPOgDApM GEfJKQMaIrSqt0k++7ZYJ6a9h29COywPv8YVV6I9FMNGATXTtXZns5Yw7YzLel8COSUX 4kbQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id p186-v6si14560876pga.2.2018.07.09.18.27.33; Mon, 09 Jul 2018 18:27:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754721AbeGJB1a (ORCPT + 12 others); Mon, 9 Jul 2018 21:27:30 -0400 Received: from mx.socionext.com ([202.248.49.38]:56089 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754597AbeGJB1W (ORCPT ); Mon, 9 Jul 2018 21:27:22 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 10 Jul 2018 10:27:21 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C278360035; Tue, 10 Jul 2018 10:27:21 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 10 Jul 2018 10:27:21 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 2BA041A11BB; Tue, 10 Jul 2018 10:27:21 +0900 (JST) From: Kunihiko Hayashi To: Liam Girdwood , Mark Brown , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v2 1/2] dt-bindings: regulator: add DT bindings for UniPhier regulator Date: Tue, 10 Jul 2018 10:27:16 +0900 Message-Id: <1531186037-16630-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531186037-16630-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1531186037-16630-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for regulators implemented in UniPhier SoCs. Signed-off-by: Kunihiko Hayashi --- .../bindings/regulator/uniphier-regulator.txt | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/regulator/uniphier-regulator.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt b/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt new file mode 100644 index 0000000..c9919f4 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/uniphier-regulator.txt @@ -0,0 +1,57 @@ +Socionext UniPhier Regulator Controller + +This describes the devicetree bindings for regulator controller implemented +on Socionext UniPhier SoCs. + +USB3 Controller +--------------- + +This regulator controls VBUS and belongs to USB3 glue layer. Before using +the regulator, it is necessary to control the clocks and resets to enable +this layer. These clocks and resets should be described in each property. + +Required properties: +- compatible: Should be + "socionext,uniphier-pro4-usb3-regulator" - for Pro4 SoC + "socionext,uniphier-pxs2-usb3-regulator" - for PXs2 SoC + "socionext,uniphier-ld20-usb3-regulator" - for LD20 SoC + "socionext,uniphier-pxs3-usb3-regulator" - for PXs3 SoC +- reg: Specifies offset and length of the register set for the device. +- clocks: A list of phandles to the clock gate for USB3 glue layer. + According to the clock-names, appropriate clocks are required. +- clock-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others +- resets: A list of phandles to the reset control for USB3 glue layer. + According to the reset-names, appropriate resets are required. +- reset-names: Should contain + "gio", "link" - for Pro4 SoC + "link" - for others + +See Documentation/devicetree/bindings/regulator/regulator.txt +for more details about the regulator properties. + +Example: + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_vbus0: regulators@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + phy { + ... + phy-supply = <&usb_vbus0>; + }; + ... + };