From patchwork Thu Aug 30 08:21:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 145528 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp536647ljw; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) X-Google-Smtp-Source: ANB0VdY+3T0/hqShevlQIk6kzgh6X1SVMjd5bHebik7K+MjD8VvyPb//1WtcfoqKj2GR9qCp5hhZ X-Received: by 2002:a62:1bc2:: with SMTP id b185-v6mr9551641pfb.170.1535617343081; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1535617343; cv=none; d=google.com; s=arc-20160816; b=VQzGkuZUE6t/hi1Vd67QU6D/MIpTrv92QKkyf0Re/HT8Aa0+ITgOXeIQVk5U1r4ewd t9sk9oIU1uDPHKdSV1wB9wAxGQh71bqTkAI1iTqCBUiEfpXL9ztyGskARnwKk/viUeCO fk42YEWtfzKd1OApCLr/dcWqAePb45uCrJGn/5rsHpPtvzcC4sYLoKSlufTsKWjlO+bd ww4DGnmfK+msZA3BPXHoIWihG3FHq8mTibhXlMviTmR9uRSRG3FVvCI4EpWFHn27p8e4 Wj2+QGwVTshnsATDhIZXyFebNB68KJzd53oI6z/pjPut3oA9EvItPCuM63iqvOu2O59s ND+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=aiVutlJ7aqahynWDVC5biR6rR6dQm8HioxsgA9FCJdCPDQ1Ckz2YULsqE8918fucfV 5En1ZOSGT6+dG6Cg12yo4T+bNjBAfD3rAM4TSxDmlirmMDl1yPap/kMPTlSP9FG1jzdM 6pzmzRuO11wqTbBkIlfesy8rnwpbZbx6yNwxL6TRRponMYotdjtej9XiCe4gQKb1xVIo /3MdcyODFHtwpbD9WsKbjxF9Ua2QXZUWgqMLvH6KcQPJPSG+UwqqpVukQXzFVJluxEJO 7hfrKTMfk1gUlHxSj4Ck8e8qTqeAt1NeN3ER6klgfCH5+HITCF354zJaqnXYCCrFCbeK U8Dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W6ReI4x1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 92-v6si6188682pli.518.2018.08.30.01.22.22; Thu, 30 Aug 2018 01:22:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W6ReI4x1; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728066AbeH3MXT (ORCPT + 32 others); Thu, 30 Aug 2018 08:23:19 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:36634 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728007AbeH3MXT (ORCPT ); Thu, 30 Aug 2018 08:23:19 -0400 Received: by mail-pg1-f193.google.com with SMTP id d1-v6so3567739pgo.3 for ; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=W6ReI4x1Bc/JmVCF489DBl573vArOUp3cJURvJx9EXcspdw1VS15ynJVuAHRR1exLj x1PjZQ87eAHftm6Wv/LTZk1KuUzvimrJ4PNbshzliEbuMSZg9ESuN57vAAc7G3iLJ4Jz CYvAr9lGj8h1xuaJO2bIJ1CHUu9Cr1+Jp9WkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3ML8nLjCbNbISUG+Te8iXuKkkqfqMMtZy3g4F+HUTCY=; b=NKSCvXiHu6tHve35jkAKNz55zc+ICDMDqsSFpv+9rzY2NOa1LHdXEj+BYa9ZMi7D6q IJCEaBDKJVvIwPrg+ivpUj7gE02yP6bCpkN8i1bB3xN61QYsQP4acPm/+Joi3+24LhcW Fkr8Yizm0cIjjxzjOCm0AlbqlEUWqsO7dMO6bVYXxQ2eaZilPjWimsgq5oIi3ii2wdjV bqld1LyJkPahSwA5ZQiLj3au9vPlM+lIlvZyeWDEmB0TLPs2rWPhmsab9XKkismrGd62 qXnhCuV+bWo4TcgNqhditCkK571xkybcTXVHsK6RDmRKZ3NW9vtUPbK6dOIb0DbrfFek TDuA== X-Gm-Message-State: APzg51AxpZbJzN6Vg48kyet2STLITZC2pYobJsDTYDI7vuQNE2K7Qs04 hDNdrpla4y1HWE/+sWRMK3s8ig== X-Received: by 2002:a62:9541:: with SMTP id p62-v6mr9585423pfd.194.1535617340445; Thu, 30 Aug 2018 01:22:20 -0700 (PDT) Received: from ubt.spreadtrum.com ([117.18.48.102]) by smtp.gmail.com with ESMTPSA id j22-v6sm8224885pfh.45.2018.08.30.01.22.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Aug 2018 01:22:19 -0700 (PDT) From: Chunyan Zhang To: Ulf Hansson , Adrian Hunter , Rob Herring Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, Orson Zhai , Baolin Wang , Billows Wu , Jason Wu , Chunyan Zhang , Chunyan Zhang Subject: [PATCH V8 5/9] mmc: sdhci: Add 32-bit block count support for v4 mode Date: Thu, 30 Aug 2018 16:21:41 +0800 Message-Id: <1535617305-16952-6-git-send-email-zhang.chunyan@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> References: <1535617305-16952-1-git-send-email-zhang.chunyan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: Chunyan Zhang Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 14 +++++++++++++- drivers/mmc/host/sdhci.h | 8 ++++++++ 2 files changed, 21 insertions(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 17345b6..604bf4c 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1073,7 +1073,19 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) /* Set the DMA boundary value and block size */ sdhci_writew(host, SDHCI_MAKE_BLKSZ(host->sdma_boundary, data->blksz), SDHCI_BLOCK_SIZE); - sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + + /* + * For Version 4.10 onwards, if v4 mode is enabled, 32-bit Block Count + * can be supported, in that case 16-bit block count register must be 0. + */ + if (host->version >= SDHCI_SPEC_410 && host->v4_mode && + (host->quirks2 & SDHCI_QUIRK2_USE_32BIT_BLK_CNT)) { + if (sdhci_readw(host, SDHCI_BLOCK_COUNT)) + sdhci_writew(host, 0, SDHCI_BLOCK_COUNT); + sdhci_writew(host, data->blocks, SDHCI_32BIT_BLK_CNT); + } else { + sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); + } } static inline bool sdhci_auto_cmd12(struct sdhci_host *host, diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index c5cc513..f7a1079 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -28,6 +28,7 @@ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS +#define SDHCI_32BIT_BLK_CNT SDHCI_DMA_ADDRESS #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) @@ -462,6 +463,13 @@ struct sdhci_host { * obtainable timeout. */ #define SDHCI_QUIRK2_DISABLE_HW_TIMEOUT (1<<17) +/* + * 32-bit block count may not support eMMC where upper bits of CMD23 are used + * for other purposes. Consequently we support 16-bit block count by default. + * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit + * block count. + */ +#define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */