From patchwork Mon Nov 19 01:01:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 151453 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp2058700ljp; Sun, 18 Nov 2018 17:01:39 -0800 (PST) X-Google-Smtp-Source: AJdET5c8ItOVft7Ye+I/WtCpanUnYwDmcEAwiDqTsMtJ2uEyenfZ7Sz+KoMAmegX91imKIwLSn+f X-Received: by 2002:a63:101d:: with SMTP id f29mr18358429pgl.38.1542589299353; Sun, 18 Nov 2018 17:01:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1542589299; cv=none; d=google.com; s=arc-20160816; b=rTno1IpWbUbyuCjUd4DoN77M1NJSmh1SaqTcJ3q5ZzNJcTgJNzj7YXmkRgKsfriE7a X5YUJIB83jqNLBhjBdnrzICuo2Qo1/OcPooeQRuDSQxpCDwITLRK8SEq26mZHAKjzVu3 O36Gl7YYe/C+fvw46uAPwYayENhEsDJsyuf1q74PE7jH3Njx7BXvKcwvTcLA2E+tokqb 3jZDmZ78wGC0+bkP+GU9Jn02ZwJ0Ifa0KmTjzRdAleV/Vj3Mwo+Gw/JS5xzT72TrKra9 QTDAfk4FwBUGiUcWlZiMCTalTBIR2/8bjYx4PsM54IWa3Im3jO1w3vUOw677vr46z2yk HRmg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=llkiED9iR0TtFZHiP1jsNA5wixWkE1OXqsRM3RgKyww=; b=PoUfhLij+JPaFdPQvxOMP5AGvzKLs6nu2TogxEOnmJDJyjove9Qvc8QXSNtyoHjQFV xgkVuHluVTPX9HL3CaEwHIAJYPA5dbaM1eobbaP46vnjs055saJOtPt9qknOyvoVj9I/ Ne09k7gF5zRMfBOWMZTmvtfWdptR2kJXO80H5MMwqZZyq32A6Yn36uKwM7VvxNDv4TOk cpYZoZB1L2WrVqa7fXcE1sPDOqv9o/kvgzzQ790+RVD79qanK8qfoxFHCYEqcIrFVwek jzFWRmr4auUgUka0po/cbFa3U+AyVCGxZ3l0OSz4FnvaFSdLuxeHZ1V5m6rhS7V6LgUP g4yQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j14si27250996pgg.44.2018.11.18.17.01.38; Sun, 18 Nov 2018 17:01:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbeKSLWd (ORCPT + 32 others); Mon, 19 Nov 2018 06:22:33 -0500 Received: from mx.socionext.com ([202.248.49.38]:40673 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727507AbeKSLWd (ORCPT ); Mon, 19 Nov 2018 06:22:33 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 19 Nov 2018 10:00:36 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 63F9C180111; Mon, 19 Nov 2018 10:00:36 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Mon, 19 Nov 2018 10:00:36 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 1066840387; Mon, 19 Nov 2018 10:00:36 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id DCB0F120455; Mon, 19 Nov 2018 10:00:35 +0900 (JST) From: Sugaya Taichi To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Cc: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland , Greg Kroah-Hartman , Daniel Lezcano , Thomas Gleixner , Russell King , Jiri Slaby , Masami Hiramatsu , Jassi Brar , Sugaya Taichi Subject: [PATCH 05/14] clocksource/drivers/timer-milbeaut: Add Milbeaut M10V timer Date: Mon, 19 Nov 2018 10:01:10 +0900 Message-Id: <1542589274-13878-6-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> References: <1542589274-13878-1-git-send-email-sugaya.taichi@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add Milbeaut M10V timer using 32bit timer in peripheral. Signed-off-by: Sugaya Taichi --- drivers/clocksource/Kconfig | 8 +++ drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-m10v.c | 146 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 155 insertions(+) create mode 100644 drivers/clocksource/timer-m10v.c -- 1.9.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 55c77e4..a278d72 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -638,4 +638,12 @@ config GX6605S_TIMER help This option enables support for gx6605s SOC's timer. +config M10V_TIMER + bool "Milbeaut M10V timer driver" if COMPILE_TEST + depends on OF + depends on ARM + select TIMER_OF + help + Enables the support for Milbeaut M10V timer driver. + endmenu diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index dd91381..8e908b4 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o obj-$(CONFIG_OWL_TIMER) += timer-owl.o +obj-$(CONFIG_M10V_TIMER) += timer-m10v.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o diff --git a/drivers/clocksource/timer-m10v.c b/drivers/clocksource/timer-m10v.c new file mode 100644 index 0000000..ff97c23 --- /dev/null +++ b/drivers/clocksource/timer-m10v.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Socionext Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "timer-of.h" + +#define FSL_TMR_TMCSR_OFS 0x0 +#define FSL_TMR_TMR_OFS 0x4 +#define FSL_TMR_TMRLR1_OFS 0x8 +#define FSL_TMR_TMRLR2_OFS 0xc +#define FSL_RMT_REGSZPCH 0x10 + +#define FSL_TMR_TMCSR_OUTL BIT(5) +#define FSL_TMR_TMCSR_RELD BIT(4) +#define FSL_TMR_TMCSR_INTE BIT(3) +#define FSL_TMR_TMCSR_UF BIT(2) +#define FSL_TMR_TMCSR_CNTE BIT(1) +#define FSL_TMR_TMCSR_TRG BIT(0) + +#define FSL_TMR_TMCSR_CSL_DIV2 0 +#define FSL_TMR_TMCSR_CSL BIT(10) + +#define M10V_TIMER_RATING 500 + +static irqreturn_t m10v_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *clk = dev_id; + struct timer_of *to = to_timer_of(clk); + u32 val; + + val = readl_relaxed(timer_of_base(to) + FSL_TMR_TMCSR_OFS); + val &= ~FSL_TMR_TMCSR_UF; + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + + clk->event_handler(clk); + + return IRQ_HANDLED; +} + +static int m10v_set_state_periodic(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = (FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL); + + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + + writel_relaxed(to->of_clk.period, timer_of_base(to) + + FSL_TMR_TMRLR1_OFS); + val |= FSL_TMR_TMCSR_RELD | FSL_TMR_TMCSR_CNTE | + FSL_TMR_TMCSR_TRG | FSL_TMR_TMCSR_INTE; + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_set_state_oneshot(struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + u32 val = (FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL); + + writel_relaxed(val, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_clkevt_next_event(unsigned long event, + struct clock_event_device *clk) +{ + struct timer_of *to = to_timer_of(clk); + + writel_relaxed(event, timer_of_base(to) + FSL_TMR_TMRLR1_OFS); + writel_relaxed((FSL_TMR_TMCSR_CSL_DIV2 * FSL_TMR_TMCSR_CSL) | + FSL_TMR_TMCSR_CNTE | FSL_TMR_TMCSR_INTE | + FSL_TMR_TMCSR_TRG, timer_of_base(to) + + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_config_clock_source(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMR_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMRLR1_OFS); + writel_relaxed(~0, timer_of_base(to) + FSL_TMR_TMRLR2_OFS); + writel_relaxed(BIT(4) | BIT(1) | BIT(0), timer_of_base(to) + + FSL_TMR_TMCSR_OFS); + return 0; +} + +static int m10v_config_clock_event(struct timer_of *to) +{ + writel_relaxed(0, timer_of_base(to) + FSL_TMR_TMCSR_OFS); + return 0; +} + +static struct timer_of to = { + .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK, + + .clkevt = { + .name = "m10v-clkevt", + .rating = M10V_TIMER_RATING, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .flags = IRQF_TIMER | IRQF_IRQPOLL, + }, +}; + +static int __init m10v_timer_init(struct device_node *node) +{ + int ret; + + to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT; + to.clkevt.set_state_oneshot = m10v_set_state_oneshot; + to.clkevt.set_state_periodic = m10v_set_state_periodic; + to.clkevt.set_next_event = m10v_clkevt_next_event; + to.of_irq.handler = m10v_timer_interrupt; + + ret = timer_of_init(node, &to); + if (ret) + goto err; + + m10v_config_clock_source(&to); + clocksource_mmio_init(timer_of_base(&to) + FSL_TMR_TMR_OFS, + node->name, timer_of_rate(&to), M10V_TIMER_RATING, 32, + clocksource_mmio_readl_down); + m10v_config_clock_event(&to); + clockevents_config_and_register(&to.clkevt, timer_of_rate(&to), + 15, 0xffffffff); + + return 0; +err: + timer_of_cleanup(&to); + return ret; +} +TIMER_OF_DECLARE(m10v_peritimer, "socionext,milbeaut-m10v-timer", + m10v_timer_init);