From patchwork Fri Dec 7 00:53:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 153081 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp53357ljp; Thu, 6 Dec 2018 16:53:27 -0800 (PST) X-Google-Smtp-Source: AFSGD/XlLJm1/GfAK5Cr94jN7qu4GQEBTINeMtMJtyhnQSmFEBwiMJD5iO+1Axq3GRHdoYvWzfzx X-Received: by 2002:a17:902:8e8b:: with SMTP id bg11mr150271plb.332.1544144007168; Thu, 06 Dec 2018 16:53:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1544144007; cv=none; d=google.com; s=arc-20160816; b=Fv+PaEULD01o8+RfeFIU7frc5FaW3/A7bhDPFOnY4jZWaxIlVFrkg9SLDqIMYPBxvU WwRjGSgAW8GYcINH65nvpkII//IEvbQap/Ljutp4nbkhdBBk8AwPLnThlPJTm0pmhCvO 4onJS6rxhsQQB/1GiI5/a8+bd3qRUjbAYaUIuBNcNsNlgyopgGMFH8mjMFKBV3piQqZj veL/NibCrRnsvRGA7dB0pLkNwNqb6pr10XR56+zYKHb2ocHjOzrgYj9sxuUuPdYy6jt3 lvrBI50QR2nw1dTH7UqmJL/RKQ7EXGvsWpKklFMO267+r1RBe3PNU1BdoEFsXAqx2xPR VLIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=001mUijwUGZrjnnwxoGQxup77y8L7aW/4oeDcCLFNbA=; b=jC2aOlP4h0+BKoXgab3om7MYEXfubZHspEYGugQJuJsI/h9H1aSShCk6sjLaf7epP8 2NDXCEYfTpoNBvo9KLpn9GzN+buez0V4f1xsAVKwAvEeXQEzNQYOxLDwtesFAO984+zo F39ek5mkRm3RoP8CNaLscs0Zh3evwTWQDhj3iuDGRJy8pVOzT+vJfm5iNvZx1cGzKkkp 4JTcWaGOqfgq04wg8sTrwcNzh2GWd8aJrrwb3I7QS/WykRCdhqdv7EGr7XgzN6H9U9k0 WUzXYJeQZpHwV2ZZiXtTTh3IwBvdx/iVHjpQOJptnHA2qhF8ocHuP5dun5jAQ+auBFze qCpA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w7si1474868pgh.560.2018.12.06.16.53.26; Thu, 06 Dec 2018 16:53:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725939AbeLGAxX (ORCPT + 31 others); Thu, 6 Dec 2018 19:53:23 -0500 Received: from mx.socionext.com ([202.248.49.38]:42327 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725950AbeLGAxV (ORCPT ); Thu, 6 Dec 2018 19:53:21 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 07 Dec 2018 09:53:19 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id A6CC060062; Fri, 7 Dec 2018 09:53:19 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Dec 2018 09:53:19 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 18FA11A1235; Fri, 7 Dec 2018 09:53:19 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Rob Herring , Mark Rutland , Masahiro Yamada Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Gustavo Pimentel , Kunihiko Hayashi Subject: [PATCH v5 1/2] dt-bindings: PCI: Add UniPhier PCIe host controller description Date: Fri, 7 Dec 2018 09:53:11 +0900 Message-Id: <1544143992-16385-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1544143992-16385-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1544143992-16385-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings for PCIe controller implemented in UniPhier SoCs when configured in Root Complex (host) mode. This controller is based on the DesignWare PCIe core. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/uniphier-pcie.txt | 81 ++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt new file mode 100644 index 0000000..1fa2c59 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie.txt @@ -0,0 +1,81 @@ +Socionext UniPhier PCIe host controller bindings + +This describes the devicetree bindings for PCIe host controller implemented +on Socionext UniPhier SoCs. + +UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and inherits +common properties defined in +Documentation/devicetree/bindings/pci/designware-pcie.txt. + +Required properties: +- compatible: Should be "socionext,uniphier-pcie". +- reg: Specifies offset and length of the register set for the device. + According to the reg-names, appropriate register sets are required. +- reg-names: Must include the following entries: + "dbi" - controller configuration registers + "link" - SoC-specific glue layer registers + "config" - PCIe configuration space +- clocks: A phandle to the clock gate for PCIe glue layer including + the host controller. +- resets: A phandle to the reset line for PCIe glue layer including + the host controller. +- interrupts: A list of interrupt specifiers. According to the + interrupt-names, appropriate interrupts are required. +- interrupt-names: Must include the following entries: + "dma" - DMA interrupt + "msi" - MSI interrupt + +Optional properties: +- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate + phys are required. +- phy-names: Must be "pcie-phy". + +Required sub-node: +- legacy-interrupt-controller: Specifies interrupt controller for legacy PCI + interrupts. + +Required properties for legacy-interrupt-controller: +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: specifies the number of cells needed to encode an + interrupt source. The value must be 1. +- interrupt-parent: Phandle to the parent interrupt controller. +- interrupts: An interrupt specifier for legacy interrupt. + +Example: + + pcie: pcie@66000000 { + compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; + status = "disabled"; + reg-names = "dbi", "link", "config"; + reg = <0x66000000 0x1000>, <0x66010000 0x10000>, + <0x2fff0000 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&sys_clk 24>; + resets = <&sys_rst 24>; + num-lanes = <1>; + num-viewport = <1>; + bus-range = <0x0 0xff>; + device_type = "pci"; + ranges = + /* downstream I/O */ + <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>; + #interrupt-cells = <1>; + interrupt-names = "dma", "msi"; + interrupts = <0 224 4>, <0 225 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ + <0 0 0 2 &pcie_intc 1>, /* INTB */ + <0 0 0 3 &pcie_intc 2>, /* INTC */ + <0 0 0 4 &pcie_intc 3>; /* INTD */ + + pcie_intc: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 226 4>; + }; + };