From patchwork Tue Jun 18 10:02:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Erwan Le Ray X-Patchwork-Id: 167128 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp4002106ilk; Tue, 18 Jun 2019 03:03:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqxsJ+hn08HYGuzYi5ov+sI3WXxm7cHeZ1/0Iij0hjWpWPg+o//P3Oea2j1+JKh7ErWj9ed/ X-Received: by 2002:a17:902:b70f:: with SMTP id d15mr30674348pls.318.1560852187527; Tue, 18 Jun 2019 03:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560852187; cv=none; d=google.com; s=arc-20160816; b=RZnk3EY4+CH4CoPmSp5sk08A06f3e2UmOD/S1vj0XochZrOff/AP9S3hl9VhGwMXhA kKmrfhJ75MJwLGZrCo5aAsycTVhZSOK4nkEZj+mWJlqZYZcsAaK+V5r8UMtDM8MZ2xso Zf/sf+UVmstOHV34BI+6agpVlreSX8wMf7DwnzuY7OybEEdXVZnfiVPOWhbs6iVkfpVD mjr6QzcjRgUh4iarEPVgH7BVbMu5GIK4EDl2KdsoeiMh+T1qr2FbAFiWMEntmVt0Yz4I aVJ/2XJIIrSfWdzW2Mek4zrYLWgO8JOT4e5gt8mpV+RrWieqnM7XUOzAHOkSXAoYR3dm f4Cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=ZNwrI9/E19QXLogxcwXLV+/wtFzsSvuPA6hnm0JPcRM=; b=HbK4k640HRahaLk0VZcJ/CU51eDgGaIs2+cg9F5OJ/VSjX7x44Ylks2WQhxwNQKPHT l7nlI0VOwzfcQ/GvnK1n+l2wb0ILs+scWPGn3uh+JemAzRYlfqQrOUGa040CEsiCYcZb qw2Pn0FDLmDYcbOeC87Y3Hxwk+AoyrEm5kZKqaRY+DZ30XWz5Ve2I2V2c6jNZYfe4XfA l7umfbVDnYpdJwiaiFmQ4vtZhESkxWCK9HznN3iZ76a4uSAr6quL3ly6Z0px1+jn9yQv mic64EE8VbcUiRwMTPIb+FMPb2uT/LkSSi7Syry890W1h2RKoP/dZuIAxatM2V06BAVT bncQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=pKMdFCu6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y62si12861616pfy.244.2019.06.18.03.03.07; Tue, 18 Jun 2019 03:03:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@st.com header.s=STMicroelectronics header.b=pKMdFCu6; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729139AbfFRKDF (ORCPT + 29 others); Tue, 18 Jun 2019 06:03:05 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:27384 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726023AbfFRKDC (ORCPT ); Tue, 18 Jun 2019 06:03:02 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5IA1kqT030835; Tue, 18 Jun 2019 12:02:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=STMicroelectronics; bh=ZNwrI9/E19QXLogxcwXLV+/wtFzsSvuPA6hnm0JPcRM=; b=pKMdFCu6z9l+iNvnnuFWzm/ITOJ4O7pD3VwiAG1XRPj/EB74vBLEw9mGVCi62jp2V5X5 RjADxoXBtw/U9b/GCXEAfxfHiMYwkJXGI5Gn6qLPyYbpQc+I0Qo6stg4MqxSDer2tBN5 L4mqGeMTarLq8Kl/+5adGTt4SDB9/1dBIKMgdYNmSS870lUw+A8L2npVXeztPIxUIRmp 1cAEHe/3YSBft1VMmwYslw9wRl3BTvDm25TYlOGgdzrrYZGmU9CmzZs6zsFXvgM4Ec9x TIpUF7DcIxoi1jwFxLdZ1vc8OlxFpsDDMs5FplvHeTTLvb5lpfNAHiRdaXy4EmSC+oy3 HA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2t68n3nv0e-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 18 Jun 2019 12:02:45 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C84553A; Tue, 18 Jun 2019 10:02:43 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A704725DD; Tue, 18 Jun 2019 10:02:43 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 12:02:43 +0200 Received: from localhost (10.201.23.31) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 18 Jun 2019 12:02:43 +0200 From: Erwan Le Ray To: Greg Kroah-Hartman , Jiri Slaby , Maxime Coquelin , "Alexandre Torgue" CC: , , , , "Erwan Le Ray" , Fabrice Gasnier Subject: [PATCH 5/5] serial: stm32: add RX and TX FIFO flush Date: Tue, 18 Jun 2019 12:02:26 +0200 Message-ID: <1560852146-3393-6-git-send-email-erwan.leray@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1560852146-3393-1-git-send-email-erwan.leray@st.com> References: <1560852146-3393-1-git-send-email-erwan.leray@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.31] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-06-18_05:, , signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Adds a flush of RX and TX FIFOs, and fixes some errors: - adds RX FIFO flush in startup fonction - removes the useless transmitter enabling in startup fonction (e.g. receiver only, see Documentation/serial/driver) - configures FIFO threshold before enabling it, rather than after - flushes both TX and RX in set_termios function Signed-off-by: Erwan Le Ray -- 1.9.1 diff --git a/drivers/tty/serial/stm32-usart.c b/drivers/tty/serial/stm32-usart.c index 4083145..21dc380 100644 --- a/drivers/tty/serial/stm32-usart.c +++ b/drivers/tty/serial/stm32-usart.c @@ -602,11 +602,11 @@ static int stm32_startup(struct uart_port *port) if (ret) return ret; - val = stm32_port->cr1_irq | USART_CR1_TE | USART_CR1_RE; - if (stm32_port->fifoen) - val |= USART_CR1_FIFOEN; - stm32_set_bits(port, ofs->cr1, val); + /* RX FIFO Flush */ + if (ofs->rqr != UNDEF_REG) + stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ); + /* Tx and RX FIFO configuration */ if (stm32_port->fifoen) { val = readl_relaxed(port->membase + ofs->cr3); val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); @@ -615,6 +615,12 @@ static int stm32_startup(struct uart_port *port) writel_relaxed(val, port->membase + ofs->cr3); } + /* RX FIFO enabling */ + val = stm32_port->cr1_irq | USART_CR1_RE; + if (stm32_port->fifoen) + val |= USART_CR1_FIFOEN; + stm32_set_bits(port, ofs->cr1, val); + return 0; } @@ -697,8 +703,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, /* Stop serial port and reset value */ writel_relaxed(0, port->membase + ofs->cr1); - cr1 = USART_CR1_TE | USART_CR1_RE; + /* flush RX & TX FIFO */ + if (ofs->rqr != UNDEF_REG) + stm32_set_bits(port, ofs->rqr, + USART_RQR_TXFRQ | USART_RQR_RXFRQ); + cr1 = USART_CR1_TE | USART_CR1_RE; if (stm32_port->fifoen) cr1 |= USART_CR1_FIFOEN; cr2 = 0;