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[209.132.180.67]) by mx.google.com with ESMTP id x9si6790638eju.147.2019.09.30.07.37.08; Mon, 30 Sep 2019 07:37:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731830AbfI3OhG (ORCPT + 27 others); Mon, 30 Sep 2019 10:37:06 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3194 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1731803AbfI3OhE (ORCPT ); Mon, 30 Sep 2019 10:37:04 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 324169B4856EE48EF227; Mon, 30 Sep 2019 22:36:58 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Mon, 30 Sep 2019 22:36:49 +0800 From: John Garry To: , , , , , CC: , , , , , , , , John Garry Subject: [RFC PATCH 5/6] perf/smmuv3: Match implementation options based on parent SMMU IIDR Date: Mon, 30 Sep 2019 22:33:50 +0800 Message-ID: <1569854031-237636-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1569854031-237636-1-git-send-email-john.garry@huawei.com> References: <1569854031-237636-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we match the implementation options based on the ACPI PLATFORM OEM ID. Since we can now match based on the parent SMMUv3 IIDR, switch to this method. Signed-off-by: John Garry --- drivers/perf/arm_smmuv3_pmu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/perf/arm_smmuv3_pmu.c b/drivers/perf/arm_smmuv3_pmu.c index 11f28ba5fae0..33d1379ae525 100644 --- a/drivers/perf/arm_smmuv3_pmu.c +++ b/drivers/perf/arm_smmuv3_pmu.c @@ -739,14 +739,10 @@ static void smmu_pmu_reset(struct smmu_pmu *smmu_pmu) smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); } -static void smmu_pmu_get_acpi_options(struct smmu_pmu *smmu_pmu) +static void smmu_pmu_get_implementation_options(struct smmu_pmu *smmu_pmu) { - u32 model; - - model = *(u32 *)dev_get_platdata(smmu_pmu->dev); - - switch (model) { - case IORT_SMMU_V3_PMCG_HISI_HIP08: + switch (smmu_pmu->parent_iidr) { + case PARENT_SMMU_IIDR_HISI_HIP08: /* HiSilicon Erratum 162001800 */ smmu_pmu->options |= SMMU_PMCG_EVCNTR_RDONLY; break; @@ -844,7 +840,7 @@ static int smmu_pmu_probe(struct platform_device *pdev) return -EINVAL; } - smmu_pmu_get_acpi_options(smmu_pmu); + smmu_pmu_get_implementation_options(smmu_pmu); /* Pick one CPU to be the preferred one to use */ smmu_pmu->on_cpu = raw_smp_processor_id();