From patchwork Mon Apr 10 13:17:59 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 97135 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp1358770qgd; Mon, 10 Apr 2017 06:19:02 -0700 (PDT) X-Received: by 10.98.93.150 with SMTP id n22mr54078074pfj.103.1491830342696; Mon, 10 Apr 2017 06:19:02 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i5si13595166pgj.223.2017.04.10.06.19.02; Mon, 10 Apr 2017 06:19:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753707AbdDJNSq (ORCPT + 24 others); Mon, 10 Apr 2017 09:18:46 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:57540 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753675AbdDJNSo (ORCPT ); Mon, 10 Apr 2017 09:18:44 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v3ADIcFN000902; Mon, 10 Apr 2017 08:18:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1491830318; bh=5065q/d0eQq5R28+owi7nnqISB40X0iHN979BIXGwHk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L4BQkHpW90MO4Uv8oYY711h+GT1IpaMbLXbvxuppu2SSMAPipMHuWsPJfxYd3i9mJ O5vwkdCIUBY7WObWLJw4VYnsdEujwlWokTWK3obTNX9IDkH3oqHXuez76mCqdaCNJR nfP4onjwaQzI4V7TtZ8YYxQp0Z0aT4ROE1ySyLaQ= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIcfs027289; Mon, 10 Apr 2017 08:18:38 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Mon, 10 Apr 2017 08:18:37 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v3ADIOM2032573; Mon, 10 Apr 2017 08:18:37 -0500 From: Kishon Vijay Abraham I To: CC: , Subject: [PATCH 08/32] phy: meson8b-usb2: fix offsets for some of the registers Date: Mon, 10 Apr 2017 18:47:59 +0530 Message-ID: <20170410131823.26485-9-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170410131823.26485-1-kishon@ti.com> References: <20170410131823.26485-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Martin Blumenstingl The register offsets for REG_DBG_UART (and all following) were off by 0x4. This was not a problem yet because these registers are currently not used by the driver. Signed-off-by: Martin Blumenstingl Reviewed-by: Jerome Brunet Signed-off-by: Kishon Vijay Abraham I --- drivers/phy/phy-meson8b-usb2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -- 2.11.0 diff --git a/drivers/phy/phy-meson8b-usb2.c b/drivers/phy/phy-meson8b-usb2.c index 33c9f4ba157d..30f56a6a411f 100644 --- a/drivers/phy/phy-meson8b-usb2.c +++ b/drivers/phy/phy-meson8b-usb2.c @@ -81,9 +81,9 @@ #define REG_ADP_BC_ACA_PIN_GND BIT(25) #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26) -#define REG_DBG_UART 0x14 +#define REG_DBG_UART 0x10 -#define REG_TEST 0x18 +#define REG_TEST 0x14 #define REG_TEST_DATA_IN_MASK GENMASK(3, 0) #define REG_TEST_EN_MASK GENMASK(7, 4) #define REG_TEST_ADDR_MASK GENMASK(11, 8) @@ -93,7 +93,7 @@ #define REG_TEST_DATA_OUT_MASK GENMASK(19, 16) #define REG_TEST_DISABLE_ID_PULLUP BIT(20) -#define REG_TUNE 0x1c +#define REG_TUNE 0x18 #define REG_TUNE_TX_RES_TUNE_MASK GENMASK(1, 0) #define REG_TUNE_TX_HSXV_TUNE_MASK GENMASK(3, 2) #define REG_TUNE_TX_VREF_TUNE_MASK GENMASK(7, 4)