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[209.132.180.67]) by mx.google.com with ESMTP id t186si12212057pfb.65.2017.05.29.23.09.28; Mon, 29 May 2017 23:09:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751080AbdE3GJY (ORCPT + 25 others); Tue, 30 May 2017 02:09:24 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:33267 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751042AbdE3GJV (ORCPT ); Tue, 30 May 2017 02:09:21 -0400 Received: by mail-pf0-f195.google.com with SMTP id f27so15623629pfe.0; Mon, 29 May 2017 23:09:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=e5dzJQpBCKnzKxYbUkAiuIcrKpyOxvrOHvSbq+KrLEg=; b=SUrD0RUMTiMIh2UhMNK3jinWzU0d79Edd/CZ+p85HLiLVCFnlaOkxvNX9qd6K8hQgn jh/ejXir12VyLzg3Sz4awyODNZCfOpX1l05cnu3MfOp9lohCSZGH4ryTfZRchpMmaXTJ 6GJT0sFdkpQasC1/BCw2UaGquIk3vqT0RJJGXPg8rJNKAfUwVHnPfbz8iBj6hSADddta kzFDDNDxJ6Zz46MtbQQgBtVdHDxVy9aLB0tDtQ6KMZOBmmvbzW0y2xeqagSd0YIzM6Yi RUYSXBlmOnywu3FwR72b+HN8L/2b38GughiErfuGjwzsoZ+5rgxR4SoCrn17HtAlY4kh 1iLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=e5dzJQpBCKnzKxYbUkAiuIcrKpyOxvrOHvSbq+KrLEg=; b=UW+2meMLgn6BlFOYhLiCtmVGR2r5lpG6qfVv1jAr74wiIsAtMcCGPaigWfHMT/Sc5I /7HTIdIqjhwvqCSL8lQCKnUrvQ5fQM4qyrLSb+754kyzi7Rgs7Sw1/P6MR72gG90NbnK I75TDO4o9k3hJ9fHShmwIVIpaL78W1ydQ+Ps+0wYWbEV/jEhXCJ4m1Dnnu05HkeMF8M9 24YmjjudldxgjI2A8aduDv+q17LeFRWRAMZwbhWnwctJ7Dr6h8VXrsM1gAAtgvYcNGpT MGt/lnYj7K92VKk2Zp4pd2Ya54AP+evdWUwKxGE5A6gjynSdjhkNPV10Dp0UM6gPZURr OSFg== X-Gm-Message-State: AODbwcBsmXivFR6110e9KMWiTRrWIW7WrPf4pc7y/EjN7UGp/AmUsjep JTfScnA414pnSQ== X-Received: by 10.98.59.2 with SMTP id i2mr21566390pfa.50.1496124560173; Mon, 29 May 2017 23:09:20 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id 65sm1586090pgf.14.2017.05.29.23.09.15 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 29 May 2017 23:09:19 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 30 May 2017 15:39:12 +0930 From: Joel Stanley To: Philipp Zabel , Rob Herring , Mark Rutland Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Benjamin Herrenschmidt , Andrew Jeffery Subject: [PATCH v2 2/2] reset: Add basic single-register reset driver Date: Tue, 30 May 2017 15:38:51 +0930 Message-Id: <20170530060851.29923-3-joel@jms.id.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170530060851.29923-1-joel@jms.id.au> References: <20170530060851.29923-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This driver is a basic single-register reset controller driver that supports clearing a single bit in a register. Signed-off-by: Joel Stanley --- v2: - Support assert-on-clear dt property - Depend on OF and MFD_SYSCON Signed-off-by: Joel Stanley --- drivers/reset/Kconfig | 7 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-basic.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 121 insertions(+) create mode 100644 drivers/reset/reset-basic.c -- 2.11.0 diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d21c07ccc94e..8560e304905c 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -28,6 +28,13 @@ config RESET_ATH79 This enables the ATH79 reset controller driver that supports the AR71xx SoC reset controller. +config RESET_BASIC + bool "Basic Reset Driver" + depends on OF && MFD_SYSCON + help + This enables a basic single-register reset controller driver that + supports clearing a single bit in a register. + config RESET_BERLIN bool "Berlin Reset Driver" if COMPILE_TEST default ARCH_BERLIN diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 02a74db94339..e8e8869e098d 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o obj-$(CONFIG_RESET_ATH79) += reset-ath79.o +obj-$(CONFIG_RESET_BASIC) += reset-basic.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o diff --git a/drivers/reset/reset-basic.c b/drivers/reset/reset-basic.c new file mode 100644 index 000000000000..5afac408295a --- /dev/null +++ b/drivers/reset/reset-basic.c @@ -0,0 +1,113 @@ +/* + * Copyright 2017 IBM Corperation + * + * Joel Stanley + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define to_basic_reset_priv(p) \ + container_of((p), struct basic_reset_priv, rcdev) + +struct basic_reset_priv { + struct regmap *regmap; + struct reset_controller_dev rcdev; + u32 reg; + bool assert_on_clear; +}; + +static int basic_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 value = priv->assert_on_clear ? 0 : BIT(id); + + regmap_update_bits(priv->regmap, priv->reg, BIT(id), value); + + return 0; +} + +static int basic_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 value = priv->assert_on_clear ? BIT(id) : 0; + + regmap_update_bits(priv->regmap, priv->reg, BIT(id), value); + + return 0; +} + +static int basic_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct basic_reset_priv *priv = to_basic_reset_priv(rcdev); + u32 mask = BIT(id); + u32 val; + + regmap_read(priv->regmap, priv->reg, &val); + + return !!(val & mask); +} + +static const struct reset_control_ops basic_reset_ops = { + .assert = basic_reset_assert, + .deassert = basic_reset_deassert, + .status = basic_reset_status, +}; + +static int basic_reset_probe(struct platform_device *pdev) +{ + struct device_node *parent_np = of_get_parent(pdev->dev.of_node); + struct basic_reset_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regmap = syscon_node_to_regmap(parent_np); + of_node_put(parent_np); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + ret = of_property_read_u32(pdev->dev.of_node, "reg", &priv->reg); + if (ret) + return ret; + + priv->assert_on_clear = of_property_read_bool(pdev->dev.of_node, + "assert-on-clear"); + + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.ops = &basic_reset_ops; + priv->rcdev.of_node = pdev->dev.of_node; + priv->rcdev.nr_resets = 32; + + return reset_controller_register(&priv->rcdev); +} + +static const struct of_device_id basic_reset_dt_match[] = { + { .compatible = "reset-basic" }, + { }, +}; + +static struct platform_driver basic_reset_driver = { + .probe = basic_reset_probe, + .driver = { + .name = "basic-reset", + .of_match_table = basic_reset_dt_match, + }, +}; +builtin_platform_driver(basic_reset_driver);