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[209.132.180.67]) by mx.google.com with ESMTP id n34si1305188pld.268.2017.06.14.20.07.01; Wed, 14 Jun 2017 20:07:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.b=QK7h2rmu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752720AbdFODGu (ORCPT + 25 others); Wed, 14 Jun 2017 23:06:50 -0400 Received: from mail-pg0-f52.google.com ([74.125.83.52]:34033 "EHLO mail-pg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752140AbdFODGs (ORCPT ); Wed, 14 Jun 2017 23:06:48 -0400 Received: by mail-pg0-f52.google.com with SMTP id v18so1273480pgb.1 for ; Wed, 14 Jun 2017 20:06:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=QK7h2rmuyNnJzQ5RJjN9cg+cX0OHLe3gklkcWiiujrkNRcKt0RfSE6qfATFkSvRvOT /Ccn8kOZtvzko5zuimuZSIFU/GDVInoh2E8Pjyb7p5r1+spIhFKYBII7IEEkwXzl2Hmf 08vDOj/INwMM5yS9+PPeW3rKtsG2ETDieVulg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=26ibPGtf3Fi4tY1hrxAlJrJuKlENMe8/xmgbIZrOl3w=; b=aZbFkEXJLWXa57pABg3tsTVlr9w+xt3XmGtbds8Ur+d0sK+lv6dIDhbhoQnunnxBL0 vc+yrv3a2keVpMniLvsLTwrYbAYs+muvTnf+w3Sw9VTjOAFR/FWVgLwV1luHQyC2TMgU n1wgEfv+TjfEZDtJueNFEO/cD9Kh7c9Bcj43cWBIPR3N+ZfspRpzcGdfIrPk4CMiq/c/ leAaqZ0G13nt8Z3PJ9UTSouNgtEizMg2CN/IDV2z3VLYg2KW0VMRKltCJpKKc2e6vx4A FCMTwn2gw5e1ntrTGSfUFca+NQSjXVBbEFVUtCtHlEsyjGwogtEeFpBgYdPLXLnZG6ZU 8djQ== X-Gm-Message-State: AKS2vOzSLPJpvFbR8op0KluHtvefiTiMPjLcBRNwDU/1/+IlXKPVRhc2 ar5BcMyVQZhcKqL2 X-Received: by 10.99.165.17 with SMTP id n17mr1737051pgf.163.1497496007725; Wed, 14 Jun 2017 20:06:47 -0700 (PDT) Received: from localhost.localdomain ([45.56.159.17]) by smtp.gmail.com with ESMTPSA id y65sm2156656pgd.33.2017.06.14.20.06.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 14 Jun 2017 20:06:47 -0700 (PDT) From: Guodong Xu To: lee.jones@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, lgirdwood@gmail.com, broonie@kernel.org, khilman@baylibre.com, arnd@arndb.de, gregory.clement@free-electrons.com, horms+renesas@verge.net.au, olof@lixom.net, thomas.petazzoni@free-electrons.com, yamada.masahiro@socionext.com, riku.voipio@linaro.org, treding@nvidia.com, krzk@kernel.org, eric@anholt.net, damm+renesas@opensource.se, ard.biesheuvel@linaro.org, linus.walleij@linaro.org, geert+renesas@glider.be Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, hw.wangxiaoyin@hisilicon.com, Leo Yan Subject: [PATCH v4 13/20] arm64: dts: hi3660: add sp804 timer node Date: Thu, 15 Jun 2017 11:04:10 +0800 Message-Id: <20170615030417.14059-14-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170615030417.14059-1-guodong.xu@linaro.org> References: <20170615030417.14059-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan The Hi3660 SoC comes with the sp804 timer in addition to the architecture timers. These ones are shutdown when reaching a deep idle states and a backup timer is needed. The sp804 belongs to another power domain and can fulfill the purpose of replacing temporarily an architecture timer when the CPU is idle. Describe it in the device tree, so it can be enabled at boot time. Suggested-by: Daniel Lezcano Acked-by: Daniel Lezcano Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a6b91f1..e138973 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -186,6 +186,17 @@ #reset-cells = <2>; }; + dual_timer0: timer@fff14000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x0 0xfff14000 0x0 0x1000>; + interrupts = , + ; + clocks = <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>, + <&crg_ctrl HI3660_OSC32K>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + i2c0: i2c@ffd71000 { compatible = "snps,designware-i2c"; reg = <0x0 0xffd71000 0x0 0x1000>;