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[209.132.180.67]) by mx.google.com with ESMTP id g77si1847898pfb.41.2017.06.16.04.56.24; Fri, 16 Jun 2017 04:56:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.b=ZP1Dfr3n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753451AbdFPL4K (ORCPT + 25 others); Fri, 16 Jun 2017 07:56:10 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:58408 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752670AbdFPL4H (ORCPT ); Fri, 16 Jun 2017 07:56:07 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v5GBtOO2007717; Fri, 16 Jun 2017 06:55:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1497614124; bh=QvXY4kJvWzLCwDf2bG+lCtMXiamQMZ+9mM0Cge8V6Jc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZP1Dfr3nm+uAzcKjnSXEfa+hzBHOSM9ci46SCVaw8sfezeGE9c84EUTlDUujkjNpf AzVAGfbLVaesch2CkzREjmsBX/KVHFQyfXQrklvzW/cP9CtnqCze6Rc45ob1JpGrHt BCecNZSeUUNFTy86dfSygFMtf8WTfqSAP5ZinhFI= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v5GBtNci016580; Fri, 16 Jun 2017 06:55:23 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 16 Jun 2017 06:55:23 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v5GBsd1e016625; Fri, 16 Jun 2017 06:55:20 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren , CC: Rob Herring , , , , , Ulf Hansson , , Russell King , Subject: [PATCH 11/12] ARM: dts: dra72-evm-revc: Add pinmux configuration for MMC Date: Fri, 16 Jun 2017 17:24:38 +0530 Message-ID: <20170616115439.8508-12-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170616115439.8508-1-kishon@ti.com> References: <20170616115439.8508-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Include dra72x-mmc-iodelay.dtsi which has pinmux and IODelay configuration values for the various MMC modes for dra72 SoC and use it in the pinctrl properties of MMC devicetree nodes present in dra72-evm-revc.dts. Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra72-evm-revc.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.11.0 diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index 5532309971ae..670c9c3e6cf0 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ #include "dra72-evm-common.dtsi" +#include "dra72x-mmc-iodelay.dtsi" #include / { @@ -94,9 +95,22 @@ }; &mmc1 { + pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; + pinctrl-0 = <&mmc1_pins_default>; + pinctrl-1 = <&mmc1_pins_hs>; + pinctrl-2 = <&mmc1_pins_sdr12>; + pinctrl-3 = <&mmc1_pins_sdr25>; + pinctrl-4 = <&mmc1_pins_sdr50>; + pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>; + pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; vqmmc-supply = <&ldo1_reg>; }; &mmc2 { + pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v"; + pinctrl-0 = <&mmc2_pins_default>; + pinctrl-1 = <&mmc2_pins_hs>; + pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>; + pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; vmmc-supply = <&evm_1v8_sw>; };