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[209.132.180.67]) by mx.google.com with ESMTP id e72si3960123pfk.514.2017.08.14.02.53.00; Mon, 14 Aug 2017 02:53:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LxcSFDsF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752956AbdHNJw6 (ORCPT + 25 others); Mon, 14 Aug 2017 05:52:58 -0400 Received: from mail-pg0-f51.google.com ([74.125.83.51]:36726 "EHLO mail-pg0-f51.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752936AbdHNJw4 (ORCPT ); Mon, 14 Aug 2017 05:52:56 -0400 Received: by mail-pg0-f51.google.com with SMTP id v77so44032865pgb.3 for ; Mon, 14 Aug 2017 02:52:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lq3KIs1DOgswtu6qE8E6iGEOaL2qSAC8H+CP6aiAxa0=; b=LxcSFDsF4bTcaAUbS80s3AqwBb8/nqEMcGmG8A/D6VP85oP3UlWMUSerqpST9yhzqZ TM1Jcmd6zzTsywaI/0Ao02QFKC0XLulmWCHoyukO3G5CwKFTYJboBo+stDyNaKSCSjQi qPVAW0Ii9SWUMlU3bjychO4vrPnFa7gvvblE8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lq3KIs1DOgswtu6qE8E6iGEOaL2qSAC8H+CP6aiAxa0=; b=CPQQJzyuvgBn9ZORMWdnXDyvRuEUE4+vUqeJkmSYu/ndLJs8Qmx8RxrVzQUpZOBNLF /JeOkSqz2+0jzzW3ftuvDPisV3r8osG6UapVccZkib4VfhkCL/qKP/YwVOTQYt/7ah7x UAxT+QHDyvvjUlT7yeRKNKikMzsnAP++aJTJu/a4xh55O1z/ov3xb6d/1OBlqkGP8I4I tJUgiN+9p6lHya5JDA3GrVa3xQPuZqTX3gbgQ1Fo0wXV/ed8uK+btCd74894AlV56Q9k io9qjIaPbjpf7S9QpqF/45UfopfOAdMsdaXYDv1V/9T2wdfGmllncJQFoYofjKTSHuoT arZQ== X-Gm-Message-State: AHYfb5h4oYzWo121E4XOeegfcbRgC/IZTM7jBJ8cJD9WvBXkBYCoNPDz skY8GoDXHIQKB73r X-Received: by 10.99.114.84 with SMTP id c20mr23385301pgn.13.1502704375777; Mon, 14 Aug 2017 02:52:55 -0700 (PDT) Received: from docularxu-ThinkPad-T440p.219.146.1.66 ([45.41.135.45]) by smtp.gmail.com with ESMTPSA id e63sm3468674pfc.24.2017.08.14.02.52.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Aug 2017 02:52:55 -0700 (PDT) From: Guodong Xu To: xuwei5@hisilicon.com, robh+dt@kernel.org, mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com, keescook@chromium.org, anton@enomsg.org, ccross@android.com, tony.luck@intel.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Leo Yan , Guodong Xu , Zhong Kaihua Subject: [PATCH v3 10/10] arm64: dts: hi3660: enable watchdog Date: Mon, 14 Aug 2017 17:50:49 +0800 Message-Id: <20170814095049.27701-11-guodong.xu@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170814095049.27701-1-guodong.xu@linaro.org> References: <20170814095049.27701-1-guodong.xu@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Leo Yan This patch is to add watchdog binding for Hi3660 on Hikey960 board. Cc: Guodong Xu Cc: Zhong Kaihua Signed-off-by: Leo Yan --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.10.2 diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 545d435..b7a90d6 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -962,5 +962,21 @@ &sdio_cfg_func>; status = "disabled"; }; + + watchdog0: watchdog@e8a06000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a06000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; + + watchdog1: watchdog@e8a07000 { + compatible = "arm,sp805-wdt", "arm,primecell"; + reg = <0x0 0xe8a07000 0x0 0x1000>; + interrupts = ; + clocks = <&crg_ctrl HI3660_OSC32K>; + clock-names = "apb_pclk"; + }; }; };