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[209.132.180.67]) by mx.google.com with ESMTP id s3si1406746pfj.46.2017.08.18.07.59.14; Fri, 18 Aug 2017 07:59:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZoAJI3I7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752555AbdHRO7J (ORCPT + 26 others); Fri, 18 Aug 2017 10:59:09 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:25739 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752113AbdHRO7G (ORCPT ); Fri, 18 Aug 2017 10:59:06 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v7IEx1OE013959; Fri, 18 Aug 2017 09:59:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1503068341; bh=4tTFgdje9oeqN70itoxCnu/zQLubUyfE+LRLxDP3kLw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZoAJI3I7uF5qYijExKpkEgxlucTUVSmdi7TQlf6SBRuwGEClXpMFm/1kSJk7Exe/E pO5Kuer2J/5JbvRV4vEcOLYYj3j0wlNFOJWF5gIf/v4FKF7FIaZiCFHLAEcJH9mMxU /fHZot4lN179E/go4sXdYtQC5G0gGBsJJ492/e+c= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEx179003207; Fri, 18 Aug 2017 09:59:01 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Fri, 18 Aug 2017 09:59:01 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Fri, 18 Aug 2017 09:59:01 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v7IEwKkB023721; Fri, 18 Aug 2017 09:58:58 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas CC: Joao Pinto , Arnd Bergmann , , , , , , Subject: [PATCH 13/18] misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR Date: Fri, 18 Aug 2017 20:28:05 +0530 Message-ID: <20170818145810.17649-14-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170818145810.17649-1-kishon@ti.com> References: <20170818145810.17649-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org pci_endpoint_test driver assumes the PCI_ENDPOINT_TEST registers will always be mapped to BAR_0. This need not always be the case like in TI's K2G where BAR_0 is mapped to PCI controller application registers. Add support so that PCI_ENDPOINT_TEST registers can be mapped to any BAR. Change the bar_size used for BAR test accordingly. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) -- 2.11.0 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 09c10f426b64..5fc0f6c6a9e5 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -90,9 +90,14 @@ struct pci_endpoint_test { /* mutex to protect the ioctls */ struct mutex mutex; struct miscdevice miscdev; + enum pci_barno test_reg_bar; }; -static int bar_size[] = { 4, 512, 1024, 16384, 131072, 1048576 }; +struct pci_endpoint_test_data { + enum pci_barno test_reg_bar; +}; + +static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 }; static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test, u32 offset) @@ -147,6 +152,9 @@ static bool pci_endpoint_test_bar(struct pci_endpoint_test *test, size = bar_size[barno]; + if (barno == test->test_reg_bar) + size = 0x4; + for (j = 0; j < size; j += 4) pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0); @@ -390,6 +398,8 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, void __iomem *base; struct device *dev = &pdev->dev; struct pci_endpoint_test *test; + struct pci_endpoint_test_data *data; + enum pci_barno test_reg_bar = BAR_0; struct miscdevice *misc_device; if (pci_is_bridge(pdev)) @@ -399,7 +409,13 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, if (!test) return -ENOMEM; + test->test_reg_bar = 0; test->pdev = pdev; + + data = (struct pci_endpoint_test_data *)ent->driver_data; + if (data) + test_reg_bar = data->test_reg_bar; + init_completion(&test->irq_raised); mutex_init(&test->mutex); @@ -441,14 +457,15 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, base = pci_ioremap_bar(pdev, bar); if (!base) { dev_err(dev, "failed to read BAR%d\n", bar); - WARN_ON(bar == BAR_0); + WARN_ON(bar == test_reg_bar); } test->bar[bar] = base; } - test->base = test->bar[0]; + test->base = test->bar[test_reg_bar]; if (!test->base) { - dev_err(dev, "Cannot perform PCI test without BAR0\n"); + dev_err(dev, "Cannot perform PCI test without BAR%d\n", + test_reg_bar); goto err_iounmap; }