| Message ID | 20170831135226.19784-8-jbrunet@baylibre.com |
|---|---|
| State | New |
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[209.132.180.67]) by mx.google.com with ESMTP id n186si6431857pgn.622.2017.08.31.06.54.12; Thu, 31 Aug 2017 06:54:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=FrTK/sBS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751873AbdHaNyK (ORCPT <rfc822;daniel.diaz@linaro.org> + 26 others); Thu, 31 Aug 2017 09:54:10 -0400 Received: from mail-wm0-f41.google.com ([74.125.82.41]:34427 "EHLO mail-wm0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751752AbdHaNwj (ORCPT <rfc822;linux-kernel@vger.kernel.org>); Thu, 31 Aug 2017 09:52:39 -0400 Received: by mail-wm0-f41.google.com with SMTP id 137so8714802wmj.1 for <linux-kernel@vger.kernel.org>; Thu, 31 Aug 2017 06:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=P6YFx55A2uXJjhi4Hsa/tYSEzAJVWkWvb4f9sTbJzXw=; b=FrTK/sBSf4v9Oz9WBguZ7kJGI9H2auYx1RGXvoS0MahCXUNAHNXvbAhj+kkIdz3EMn nt+s1U7a1KD9I5oJhPOxSijDP2eTQO9Tr6ebdQXR6xwy1VQksAKc2fynD1XxK+HT+zh7 1qtdNLfygl4TgopSL92WF2kcn0/YCALzPjd/1D+ZQFGUvcnWp3V2xc9wSB++Oln3tukO xSqQbMUk9UeEuJ0gKBwq8qun9IeJ6LGLrhqNqem3fyhVwLnVP9Wuj+bg3iYNZE8KWgQT MKJ4CoR3U5r1KXssLJkcGoMkbqXxfe/IS127dGHJbxUZwOMjUmfqUybUJF6Jiwj3sFv8 YzHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=P6YFx55A2uXJjhi4Hsa/tYSEzAJVWkWvb4f9sTbJzXw=; b=bNmgQXBLaetIrnm+EzWAKBqI6sY1gZWDtKeYwD2cV2scP8EyTxguL3f+KEtGaT6oyv jjMM7DP1YNejm1ytrD2tnuyIdTt4M4bh0FXe7blpVS+xZRWd/Bb6DjAmoGdVc4zl2Xa6 c2BUiqpTXPr/PbOtdMolPvojWGf3IZLH+2gf4hYwM2TOjlQ6wV14lJXjt8WiMTKZDD6y bcvWw/AYncQQoOxgTNA6CO3lcEECG3b7LB54Te9Esco9B+cvpy+tvJOfGVr5S8AENvWZ gYVvNvrUq0q7bncMGqU5ZOxsN5I304a3WQoZP3bMzQictR6MJz/pq/kIDbhb42IP18E+ uW6A== X-Gm-Message-State: AHPjjUhzhI38U1FBgyGuPhtMRT/24rP9UZGVMIPPB6z2a5q0MTwofG5k O94g5gfhDkf4SgxR X-Google-Smtp-Source: ADKCNb58/1kL+VR8MO+cmUit2TwBRjO3ozyefvFfYRQwwsytKdgyxQXco8BdXnbhVQqAK/hmvGv/AQ== X-Received: by 10.28.221.132 with SMTP id u126mr677595wmg.48.1504187558203; Thu, 31 Aug 2017 06:52:38 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id z1sm147959wmz.45.2017.08.31.06.52.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 31 Aug 2017 06:52:37 -0700 (PDT) From: Jerome Brunet <jbrunet@baylibre.com> To: Kevin Hilman <khilman@baylibre.com>, Carlo Caione <carlo@caione.org> Cc: Jerome Brunet <jbrunet@baylibre.com>, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] ARM64: dts: meson-gxbb: p20x: enable sdcard UHS modes Date: Thu, 31 Aug 2017 15:52:24 +0200 Message-Id: <20170831135226.19784-8-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170831135226.19784-1-jbrunet@baylibre.com> References: <20170831135226.19784-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: <linux-kernel.vger.kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org |
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[v3,1/9] ARM64: dts: meson-gx: Use correct mmc clock source 0
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi index 704b214e8894..23c08c3afd0a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi @@ -226,6 +226,9 @@ bus-width = <4>; cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; max-frequency = <100000000>; disable-wp;
Enable sdcard UHS modes, up to SDR50, on p20x based boards. While the s905 supports SDR104 mode, it appears that the PCB of p20x based boards can't cope with a rate as high as 200Mhz. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.9.5