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[209.132.180.67]) by mx.google.com with ESMTP id e1si4654106pgq.168.2017.09.18.06.46.52; Mon, 18 Sep 2017 06:46:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=Gz4J7cW7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755004AbdIRNqu (ORCPT + 26 others); Mon, 18 Sep 2017 09:46:50 -0400 Received: from mail-wr0-f174.google.com ([209.85.128.174]:43210 "EHLO mail-wr0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932687AbdIRNqR (ORCPT ); Mon, 18 Sep 2017 09:46:17 -0400 Received: by mail-wr0-f174.google.com with SMTP id a43so544503wrc.0 for ; Mon, 18 Sep 2017 06:46:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=r/zvGjiMzT2GM5av7cyQS7Gvu/XjANYw4OUvXWzraqM=; b=Gz4J7cW7LZO0xc06fhEn+XUe2tSkDmro7y0EkjWaWxlNb1ws5lcD8XM5qsQK9eHaD/ OaY5GNcGIV0OhBB0S7Px9DaxouRBUNU5OgjgmIIsN459gRNV3+R2JHr3EoA0GbIv3k+o M0Ry0cXGe3PT91vryVZtXgtsFpm3YRgx9QFDarPvNmXsPDvc1rkw285xU0Um0hNu2aTh 7vlL2ewD1/qjfRwJ/+eGQmQPv6+2Fue97LEqPncqwYLU5bIXNSBLh64msluqc5hIGEVl ATPUBMva3VQAXXQ5MReQ92Vwvekj4Fn/yzFcbi2F8CSkcthjbuKKIQqTMjMdNK5in2d1 6YAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r/zvGjiMzT2GM5av7cyQS7Gvu/XjANYw4OUvXWzraqM=; b=b8UCvA8M7p1JDpb7dygVAUBbvh5wElSP5NFYeRDoos1qU5mEkUKfrnUXnZpCMD+D5s zGyoaB7ydBFOwiygeksSE6I7OK3b7YVC3pnzh5xJE5Qu9T8tTYUS+o85+RatJRNrgp/J KGDkAnEMqjXz6NrKKO9UCPVh4T9Hnfwd/LnsoND1KP/318WL+QbXbRhNloB9Rzm2re1s A2WXTwXT7zIYG8pBMT/nNFYBLEOyUfLgIjPJe4hhHItzUa78YGKXomvKf/okOKIjh0/V SXu56CZwc/fs6hL+HbEoIaxI/jOQvyKh2rxjos4RNA0UbahYKKvjn50jeWsUvLTPnK5s Bt6g== X-Gm-Message-State: AHPjjUg7xmAyrC8R4dZ95I8UqPB7Mz6R/QBGbJ7FfnsNzMEJlTfmhx9E wL8RC5lHAFlNP4XQ X-Google-Smtp-Source: AOwi7QD7NhV5zDbzrJbhH/J0yNIThvodOAkN/cYBtvwszYIEe7VxbvR7gGNkAWtzwQ9mcAg/LuDHJQ== X-Received: by 10.223.161.137 with SMTP id u9mr14967752wru.280.1505742376200; Mon, 18 Sep 2017 06:46:16 -0700 (PDT) Received: from localhost.localdomain ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id n29sm6888585wmi.46.2017.09.18.06.46.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Sep 2017 06:46:15 -0700 (PDT) From: Jerome Brunet To: Marc Zyngier , Thomas Gleixner , Jason Cooper , Heiner Kallweit Cc: Jerome Brunet , Kevin Hilman , Carlo Caione , linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/2] dt-bindings: interrupt-controller: add DT binding for meson GPIO interrupt controller Date: Mon, 18 Sep 2017 15:46:09 +0200 Message-Id: <20170918134610.17743-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170918134610.17743-1-jbrunet@baylibre.com> References: <20170918134610.17743-1-jbrunet@baylibre.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This commit adds the device tree bindings description for Amlogic's GPIO interrupt controller available on the meson8b, gxbb and gxl SoC families Cc: Heiner Kallweit Signed-off-by: Jerome Brunet --- .../amlogic,meson-gpio-intc.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt -- 2.13.5 diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt new file mode 100644 index 000000000000..633e21ce4b17 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -0,0 +1,35 @@ +Amlogic meson GPIO interrupt controller + +Meson SoCs contains an interrupt controller which is able to watch the SoC +pads and generate an interrupt on edge or level. The controller is essentially +a 256 pads to 8 GIC interrupt multiplexer, with a filter block to select edge +or level and polarity. It does not expose all 256 mux inputs because the +documentation shows that the upper part is not mapped to any pad. The actual +number of interrupt exposed depends on the SoC. + +Required properties: + +- compatible : must have "amlogic,meson8-gpio-intc” and either + “amlogic,meson8b-gpio-intc” for meson8b SoCs (S805) or + “amlogic,meson-gxbb-gpio-intc” for GXBB SoCs (S905) or + “amlogic,meson-gxl-gpio-intc” for GXL SoCs (S905X, S912) +- interrupt-parent : a phandle to the GIC the interrupts are routed to. + Usually this is provided at the root level of the device tree as it is + common to most of the SoC. +- reg : Specifies base physical address and size of the registers. +- interrupt-controller : Identifies the node as an interrupt controller. +- #interrupt-cells : Specifies the number of cells needed to encode an + interrupt source. The value must be 2. +- meson,channel-interrupts: Array with the 8 upstream hwirq numbers. These + are the hwirqs used on the parent interrupt controller. + +Example: + +gpio_interrupt: interrupt-controller@9880 { + compatible = "amlogic,meson-gxbb-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x9880 0x0 0x10>; + interrupt-controller; + #interrupt-cells = <2>; + meson,channel-interrupts = <64 65 66 67 68 69 70 71>; +};