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[209.132.180.67]) by mx.google.com with ESMTP id o20si413140pli.593.2017.09.20.21.27.42; Wed, 20 Sep 2017 21:27:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=TzH0sKbH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751775AbdIUE1l (ORCPT + 26 others); Thu, 21 Sep 2017 00:27:41 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:34525 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751735AbdIUE1i (ORCPT ); Thu, 21 Sep 2017 00:27:38 -0400 Received: by mail-pg0-f65.google.com with SMTP id u18so2795797pgo.1; Wed, 20 Sep 2017 21:27:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LynmDiW2yu969B2RaKDWO/+SAdOqh+VivvWviNFvFp4=; b=TzH0sKbH4nlrRoqrS6IiR5CpNHY0a5/LLGBaOGEt1LqqHeV7UucyZDPO6eTEJmlMnz KPaDVA5xZzzR1+o9yadCz3oElHQOsFqu7/HrurrdhEVWhmaggbeFpM/eDfVTGONcOBJq A7M7DxLVGcZxKLgUaFLr3dHR+Lz26WhvEYt1mSjBJGZNehmRAjITkNVWJofYM0XBy0IH BHIgPHdmzxcbY3NpUY2EcVrQ9IBw3o2E4pRgvw3+dgOLlHQ/QCjab+F8QGM3HX+bOKVB dsjvzW3zZSKlPISBl7QgAV4R0JbT7NDWmuySvTJTZLyjz8TId/RowAxT0hNSNUBaCZjU 5QTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=LynmDiW2yu969B2RaKDWO/+SAdOqh+VivvWviNFvFp4=; b=N7bOY4V5Q1tphXW1p5MWiRB03FokjwC7+xv50QM9y0nMIvVuUEOd/vSOM5VChYP5xm F1ppZganrQ0QMiYVMQaFJJxvm7ba0FeKidsiNNN44ZPLOeMiebB4EHOOVTzEbwtZSJkN /Obf8wLamWQaz96uHIhPpmcuDlwHDrGLWpiN2N28p43cKnYDG70jIdf7DpxavRkJha81 jbi1VnMoxOcd72qvnJ7BQadZ/bUxCKMZQEOBPnjAzPKlC5cEDezERl/KPilxxKa+Ayiw k1qzqfNt3aI6elnYec66PynqQ4LYK/A0rDuT1tSqq0A/sHzPGmzguqYGh6oQ56v1Vgvr ltHw== X-Gm-Message-State: AHPjjUhDNuDQNrdOeBaUSFBiaXfznnsgRYpMWeCM2WzXsP6yWGDkLfhB TaH64CQK2fBouqubLGiUhEI= X-Google-Smtp-Source: AOwi7QB1JXS8fapXZcSz94sWrx9UL2CRYFn39T+IQ+2a1nxZc8JtKpiX7X/182aHCk1zv3qQxAPrPQ== X-Received: by 10.98.211.76 with SMTP id q73mr4354442pfg.348.1505968057698; Wed, 20 Sep 2017 21:27:37 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id w90sm705502pfi.80.2017.09.20.21.27.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Sep 2017 21:27:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 21 Sep 2017 13:57:28 +0930 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v2 4/5] clk: aspeed: Register gated clocks Date: Thu, 21 Sep 2017 13:56:40 +0930 Message-Id: <20170921042641.7326-5-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170921042641.7326-1-joel@jms.id.au> References: <20170921042641.7326-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The majority of the clocks in the system are gates paired with a reset controller that holds the IP in reset. This borrows from clk_hw_register_gate, but registers two 'gates', one to control the clock enable register and the other to control the reset IP. This allows us to enforce the ordering: 1. Place IP in reset 2. Enable clock 3. Delay 4. Release reset There are some gates that do not have an associated reset; these are handled by using -1 as the index for the reset. Signed-off-by: Joel Stanley --- drivers/clk/clk-aspeed.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 19531798e040..dec9db4ec47b 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -191,6 +191,108 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val) mult, div); } +static int aspeed_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + u32 rst = BIT(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); + + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0); + + if (gate->reset_idx >= 0) { + /* Delay 10ms */ + /* TODO: can we sleep here? */ + msleep(10); + + /* Take IP out of reset */ + regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = BIT(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + /* Disable clock */ + regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk); + + spin_unlock_irqrestore(gate->lock, flags); +} + +static int aspeed_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = BIT(gate->clock_idx); + u32 reg; + + regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); + + return (reg & clk) ? 0 : 1; +} + +static const struct clk_ops aspeed_clk_gate_ops = { + .enable = aspeed_clk_enable, + .disable = aspeed_clk_disable, + .is_enabled = aspeed_clk_is_enabled, +}; + +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_clk_gate_ops; + init.flags = flags | CLK_IS_BASIC; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + static int __init aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; @@ -200,6 +302,7 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) struct regmap *map; struct clk_hw *hw; u32 val, rate; + int i; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -269,6 +372,31 @@ static int __init aspeed_clk_probe(struct platform_device *pdev) &aspeed_clk_lock); aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + /* There are a number of clocks that not included in this driver as + * more information is required: + * D2-PLL + * D-PLL + * YCLK + * RGMII + * RMII + * UART[1..5] clock source mux + */ + + for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { + const struct aspeed_gate_data *gd; + + gd = &aspeed_gates[i]; + aspeed_clk_data->hws[ASPEED_CLK_GATES + i] = + aspeed_clk_hw_register_gate(NULL, gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + CLK_GATE_SET_TO_DISABLE, + &aspeed_clk_lock); + } + return 0; };