From patchwork Mon Oct 23 18:56:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 116854 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4971016qgn; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) X-Received: by 10.159.194.196 with SMTP id u4mr11071492plz.49.1508785134163; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508785134; cv=none; d=google.com; s=arc-20160816; b=lbFi5mC+wvnY+aN9HU/YX1FU8VCHXCdk+VVjFbks5jl0R+OuzfIn9d4tSOav5/LiW7 5r8Kvo/WVupN/NxWPSEHmze6rXLW/R+Dbq4ZMK56GWE+hVUrNyA0iWjK8Q+qQLZSoG5k 3m1xOTUIHAr7CqfJPvQfgmyaE8l+gMOt9xVbQgPUa6awJszk4FtFy5JAzqX/3XlseiOy 9b7HZOZvyLXfiZp7kTdr9YZl7YWNJfH9AEIpz0mnXcsb8urm4NZbfETZeh+wFSzW7P8x J8nD8BZrC+C5hEB3DEe/EC19TLL07TXniQ1QHpGIjv02QH6rXni0nKXbfkpup/ANZn1Q FVsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=j8GEVrWze93QFy0L7dEtpJxLh46LdDvAW7WyRHVzh+JbbJv1XaDmcEqSoD681VZIAx IOwxNX0fYX7u55oY9keGQCDGdjx+sW4RNcB0ofobIqA9QynVeTAPupuGDJYnKceDPz/A VC2DsIux/jc7IkKObefzwGWwTY9Ad+oUYIASDeRb4UdHoiCpkH/SxtgaDoRsyu15esOw R37F1I6rS4T1UDGQdOtObfzMBlQd6dpR6D1KI9hBPOEbRZQkSx6uGJPoOUTM50r2JF1f WEF52Vni7BP3KYe6/M0EBt/7lTbtLpqg0QGRVo7IIB/qfigASO97I2OxfoYPx+GtrK+Z ffWQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=jmxngEOT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay2si1564297plb.434.2017.10.23.11.58.53; Mon, 23 Oct 2017 11:58:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=jmxngEOT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751943AbdJWS6v (ORCPT + 27 others); Mon, 23 Oct 2017 14:58:51 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:45424 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751854AbdJWS6o (ORCPT ); Mon, 23 Oct 2017 14:58:44 -0400 Received: by mail-wm0-f66.google.com with SMTP id q124so11438611wmb.0; Mon, 23 Oct 2017 11:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=jmxngEOTCtyue3/wmSbd1hctYksbXzzxRLJ3VjXoGzO68S4+iC0jlH71P8JlnLtudN 40blMdj8L1V1u0PmhlLktXIEIxSqnLFfBwHnd6VHwyc0Lw25y3ineH+TOPQ1B9ubZ+S9 pzFcHzUpLxOGu2M8axcpA2tS6+uDsc+JJb3kyTJgfdApPGJL9zJEAk55h4yZPEBu2afF rY5fJqi69dpuIgGxRGzVBpbIY8R0BvUYlwKSTZxPbI0zrUVPRFE+/cfeLNOoU88pju+x OhuQVV3TySxZKJBmreHBlf98SPw/qeTguhKbuo6IMAUacc4BfseXHKW3BhCCq/cJZQj3 UEkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6LIXNk6ibZItomYu8z67F1aDztDGqA+I7XIzZW7LH1c=; b=Nt+Pngyi9/QnhNrQ9hiizlnCozj/p9NTX9f7U18r2EayCKS68wx//FSnTyjgjVJDby rhVMKwxICtzdiwzOhKYzvJGjARB2EIpOaCDAoIqRJ+mA0CwYbeBwQ67O5bbZO572TsYS vPAYBoBdlB4SfTKnQiRZ15FvVggR2os1vzdAeHM5XCmzBiIe0OCsnQIy7AgyhjqVKbxS KrRtI1BE9l89M7bVyXiuFHJQ3JJZAbjgVFGqLS2RXDGhG/uX3gsYJtm22OwwRixyNm6o 3DZBMca2REabQLBpL2OvxptvGHV350Ew34qxXCTbrREByh7gd3HnhvB/BIhBGbbNeIN4 l2Yw== X-Gm-Message-State: AMCzsaV1JtNhaKmSpC4YYwb6x6SyIrDSk0vGBYL2jrx1qq7X77e6rdqO fP2wCh3Gs7veu+iN8N/192s= X-Google-Smtp-Source: ABhQp+RChafEyZ2wQdPMqPWc9qp91mDAssfsGwZkAG1tgkdZDYLq3G9GWt+K+9Bd7ZJaseG587fktA== X-Received: by 10.28.7.78 with SMTP id 75mr6068092wmh.31.1508785122939; Mon, 23 Oct 2017 11:58:42 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id s196sm5370490wmb.26.2017.10.23.11.58.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 11:58:42 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com, peppe.cavallaro@st.com, alexandre.torgue@st.com, andrew@lunn.ch, f.fainelli@gmail.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v8 02/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY Date: Mon, 23 Oct 2017 20:56:18 +0200 Message-Id: <20171023185626.31793-3-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171023185626.31793-1-clabbe.montjoie@gmail.com> References: <20171023185626.31793-1-clabbe.montjoie@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch add documentation about the MDIO switch used on sun8i-h3-emac for integrated PHY. Signed-off-by: Corentin Labbe --- .../devicetree/bindings/net/dwmac-sun8i.txt | 139 +++++++++++++++++++-- 1 file changed, 127 insertions(+), 12 deletions(-) -- 2.13.6 diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt index 725f3b187886..3e37db10fa02 100644 --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac. Please see stmmac.txt for the other unchanged properties. Required properties: -- compatible: should be one of the following string: +- compatible: must be one of the following string: "allwinner,sun8i-a83t-emac" "allwinner,sun8i-h3-emac" "allwinner,sun8i-v3s-emac" "allwinner,sun50i-a64-emac" - reg: address and length of the register for the device. - interrupts: interrupt for the device -- interrupt-names: should be "macirq" +- interrupt-names: must be "macirq" - clocks: A phandle to the reference clock for this device -- clock-names: should be "stmmaceth" +- clock-names: must be "stmmaceth" - resets: A phandle to the reset control for this device -- reset-names: should be "stmmaceth" +- reset-names: must be "stmmaceth" - phy-mode: See ethernet.txt - phy-handle: See ethernet.txt - #address-cells: shall be 1 @@ -39,23 +39,38 @@ Optional properties for the following compatibles: - allwinner,leds-active-low: EPHY LEDs are active low Required child node of emac: -- mdio bus node: should be named mdio +- mdio bus node: with compatible "snps,dwmac-mdio" Required properties of the mdio node: - #address-cells: shall be 1 - #size-cells: shall be 0 -The device node referenced by "phy" or "phy-handle" should be a child node +The device node referenced by "phy" or "phy-handle" must be a child node of the mdio node. See phy.txt for the generic PHY bindings. -Required properties of the phy node with the following compatibles: +The following compatibles require that the emac node have a mdio-mux child +node called "mdio-mux": + - "allwinner,sun8i-h3-emac" + - "allwinner,sun8i-v3s-emac": +Required properties for the mdio-mux node: + - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux" + - one child mdio for the integrated mdio with the compatible + "allwinner,sun8i-h3-mdio-internal" + - one child mdio for the external mdio if present (V3s have none) +Required properties for the mdio-mux children node: + - reg: 1 for internal MDIO bus, 2 for external MDIO bus + +The following compatibles require a PHY node representing the integrated +PHY, under the integrated MDIO bus node if an mdio-mux node is used: - "allwinner,sun8i-h3-emac", - "allwinner,sun8i-v3s-emac": + +Required properties of the integrated phy node: - clocks: a phandle to the reference clock for the EPHY - resets: a phandle to the reset control for the EPHY +- Must be a child of the integrated mdio -Example: - +Example with integrated PHY: emac: ethernet@1c0b000 { compatible = "allwinner,sun8i-h3-emac"; syscon = <&syscon>; @@ -72,13 +87,113 @@ emac: ethernet@1c0b000 { phy-handle = <&int_mii_phy>; phy-mode = "mii"; allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + phy-is-integrated; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +Example with external PHY: +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-h3-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + allwinner,leds-active-low; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; + + mdio-mux { + compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"; + #address-cells = <1>; + #size-cells = <0>; + + int_mdio: mdio@1 { + compatible = "allwinner,sun8i-h3-mdio-internal"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + int_mii_phy: ethernet-phy@1 { + reg = <1>; + clocks = <&ccu CLK_BUS_EPHY>; + resets = <&ccu RST_BUS_EPHY>; + }; + }; + ext_mdio: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + ext_rgmii_phy: ethernet-phy@1 { + reg = <1>; + }; + }: + }; +}; + +Example with SoC without integrated PHY + +emac: ethernet@1c0b000 { + compatible = "allwinner,sun8i-a83t-emac"; + syscon = <&syscon>; + reg = <0x01c0b000 0x104>; + interrupts = ; + interrupt-names = "macirq"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + #address-cells = <1>; + #size-cells = <0>; + + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + mdio: mdio { + compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; - int_mii_phy: ethernet-phy@1 { + ext_rgmii_phy: ethernet-phy@1 { reg = <1>; - clocks = <&ccu CLK_BUS_EPHY>; - resets = <&ccu RST_BUS_EPHY>; }; }; };