From patchwork Mon Oct 30 06:02:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 117443 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2190051qgn; Sun, 29 Oct 2017 23:03:43 -0700 (PDT) X-Google-Smtp-Source: ABhQp+QN9tlUfOSxFR/se7P3fKiPL2OME590MQW8BSpoaFm7+o6CPjeWRlJzXRUFiY23MxuzPpPt X-Received: by 10.98.205.68 with SMTP id o65mr7727221pfg.117.1509343423299; Sun, 29 Oct 2017 23:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509343423; cv=none; d=google.com; s=arc-20160816; b=Yh2usd5OVHwkubNNR8BJpsNBEDxokq/6ERKW+IQ+TFqi3sVNvlQNKpZXPfEqFMPQDt faWtV44DyJAzk5k4bMB9p1xkYYU38MFp17PY8tLp5RRpG939Ba6K1TBS3+cqrZ/01Bmj jbVgZNEh+wkjSnV/S68a6FrxuRAIM3fajxM+O3RT7AOjEvd195QmpbpDGwQqhlYeWkfc RPZrXqX2O6DWf6Zzny9+F19ZLX4o0wD4/b86s56fhwlWhur5KNuBxM5eFS3JRxn/liZ6 P3Tm/xPjl7tpme/dPhn1VRKaacBtcGprMVn1bBFBUkRN2h4lBENhn67TILfcL28QAJX5 aFgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=Uk79O6/FLTYDZYkocdHwZgqvc5OAQl7TXnNCkHtTQ6Y=; b=rmpWaeJLxnX5n+kVtQlR212BO5fag3/zx7w+CHxlKaFhHmvb/g5vDZQ8+uRY1Ll9ax JHErXFAodRgRDf6sLobQctaXntzKRLi9vr9h/jgKMG5paBc2DabwnkfYltdRqlI3gnX7 JplHLb8XsoAdSlXfp97wK07I2dR93CYhAKPdWCZhM559wFM/v+gh8nf2B3eqmoqD8FJC DmubnYKbeDYtcrWwUHkWO/nHQzi6OlWZrnZHQnYcvLhyQYX2QeFonHNF8nRSIJM6pHqP 5bhYXKTwyKiv9xYOEv6AgJ+KWTxsHAtqub+zdqW/9yjaXI+pkFV+yrqrEBMlJsQgGBf9 Xo6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=mctb8SdU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r10si9246711pge.285.2017.10.29.23.03.43; Sun, 29 Oct 2017 23:03:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=mctb8SdU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752341AbdJ3GDm (ORCPT + 27 others); Mon, 30 Oct 2017 02:03:42 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:48642 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752303AbdJ3GDi (ORCPT ); Mon, 30 Oct 2017 02:03:38 -0400 Received: by mail-pg0-f65.google.com with SMTP id v78so10677285pgb.5; Sun, 29 Oct 2017 23:03:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=Uk79O6/FLTYDZYkocdHwZgqvc5OAQl7TXnNCkHtTQ6Y=; b=mctb8SdUgYA2jUgzJEDptyoqc6/VNLQjIvtzI6rw0pn8CpEfueipmoTBG0ARS60rWC t6fYlge3amdl3sTUs+WwLmFcoFUFbrXb4kflraoCdRoyqNRyZV1RA6+dwVNLGmkVHZ7E 9aln07mSTdGO8ij0ZrcETMteTlXpptX1nyIFJYZVHICwc/3NyBKvHZhOM7I34k0MWeXE wa5Kdb91udLRSIxuevJuAw4OqVuCDgYbBQFiGIcFFaINT9tonkoLkcxyPa/rnpvG/xjb TwzI0U9lrfePW+mf00xoqLxAjN0BAjkHfk8BQklzGLNcU5UWmhTs2fVpzvkAlRMhchyx SP8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=Uk79O6/FLTYDZYkocdHwZgqvc5OAQl7TXnNCkHtTQ6Y=; b=oebXnOczT8TStLFVYKOYeFsW2Yb0MPpMlx//XzyGTATKQB05+cy78o8mXzPiuH8MWd gjJn+E8xenEZGH9/jCz9lZuOF3syOeJx1h8vmlZzwSKi9zKIx0i4LVRuOlFPgs8dEYKo xTrdXSJUPGmyphaJ3AUwV35um+NqU+X8fpH+wxXLC+t5yL4fSwKU8QXZv9TBMhfkw1s8 D8LwFK3pKa3CbL9MA2EWH5+ZQtC/JLX8WCGKCVqDA3JeCgt8t2ix8Q5nCozwSiCbPkF0 rHQ5NNjBqCxk/aanZPTe/gUbZwZ2jZWio4fGH5bNG7jzqQwXtfV0kD3Dmm1o964zMU61 9OJg== X-Gm-Message-State: AMCzsaW6jnV49CIYjH/YQrhHJkrFUgWJkAxVtnek15WUsHHzTH3bEJzh YcgHZ50H5UMxjC1fyUifmGY= X-Received: by 10.98.189.23 with SMTP id a23mr7792223pff.124.1509343417647; Sun, 29 Oct 2017 23:03:37 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id a13sm8698030pgq.10.2017.10.29.23.03.31 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 29 Oct 2017 23:03:36 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 30 Oct 2017 16:33:28 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v5 3/5] clk: aspeed: Add platform driver and register PLLs Date: Mon, 30 Oct 2017 16:32:48 +1030 Message-Id: <20171030060250.701-4-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171030060250.701-1-joel@jms.id.au> References: <20171030060250.701-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This registers a platform driver to set up all of the non-core clocks. The clocks that have configurable rates are now registered. Signed-off-by: Joel Stanley -- v5: - Remove eclk configuration. We do not have enough information to correctly implement the mux and divisor, so it will have to be implemented in the future v4: - Add eclk div table to fix ast2500 calculation - Add defines to document the BIT() macros - Pass dev where we can when registering clocks - Check for errors when registering clk_hws v3: - Fix bclk and eclk calculation - Separate out ast2400 and ast25000 for pll calculation --- drivers/clk/clk-aspeed.c | 130 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) -- 2.14.1 Reviewed-by: Andrew Jeffery diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index a8da411326e9..8bf3f3767560 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -114,6 +116,18 @@ static const struct aspeed_gate_data aspeed_gates[] = { [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ }; +static const struct clk_div_table ast2500_mac_div_table[] = { + { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + static const struct clk_div_table ast2400_div_table[] = { { 0x0, 2 }, { 0x1, 4 }, @@ -179,6 +193,122 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; + +static const struct aspeed_clk_soc_data ast2500_data = { + .div_table = ast2500_div_table, + .mac_div_table = ast2500_mac_div_table, + .calc_pll = aspeed_ast2500_calc_pll, +}; + +static const struct aspeed_clk_soc_data ast2400_data = { + .div_table = ast2400_div_table, + .mac_div_table = ast2400_div_table, + .calc_pll = aspeed_ast2400_calc_pll, +}; + +static int aspeed_clk_probe(struct platform_device *pdev) +{ + const struct aspeed_clk_soc_data *soc_data; + struct device *dev = &pdev->dev; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + /* SoC generations share common layouts but have different divisors */ + soc_data = of_device_get_match_data(dev); + if (!soc_data) { + dev_err(dev, "no match data for platform\n"); + return -EINVAL; + } + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_MISC_CTRL, &val); + if (val & UART_DIV13_EN) + rate = 24000000 / 13; + else + rate = 24000000; + /* TODO: Find the parent data for the uart clock */ + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* + * Memory controller (M-PLL) PLL. This clock is configured by the + * bootloader, and is exposed to Linux as a read-only clock rate. + */ + regmap_read(map, ASPEED_MPLL_PARAM, &val); + hw = soc_data->calc_pll("mpll", val); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; + + /* SD/SDIO clock divider (TODO: There's a gate too) */ + hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, + soc_data->mac_div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, + soc_data->div_table, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + return 0; +}; + +static const struct of_device_id aspeed_clk_dt_ids[] = { + { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, + { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, + { } +}; + +static struct platform_driver aspeed_clk_driver = { + .probe = aspeed_clk_probe, + .driver = { + .name = "aspeed-clk", + .of_match_table = aspeed_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_clk_driver); + static void __init aspeed_ast2400_cc(struct regmap *map) { struct clk_hw *hw;