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[209.132.180.67]) by mx.google.com with ESMTP id j125si10107620pfg.602.2017.10.29.23.04.01; Sun, 29 Oct 2017 23:04:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=C+siZa6L; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752416AbdJ3GEA (ORCPT + 27 others); Mon, 30 Oct 2017 02:04:00 -0400 Received: from mail-pg0-f66.google.com ([74.125.83.66]:55164 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752393AbdJ3GD5 (ORCPT ); Mon, 30 Oct 2017 02:03:57 -0400 Received: by mail-pg0-f66.google.com with SMTP id l24so10669215pgu.11; Sun, 29 Oct 2017 23:03:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=b9m1nmaWtWBwif+xXJu8UuQzESZbAhj4RM3etQ7FUiM=; b=C+siZa6LS6+EmC6xEqoIo6+mnu7vsUyCNDPH3Q6JOX119Kh2pddAVWTIU6vhS+Ty61 zGA98koFcnOtFTCZC6DYhvkWWWoz7uZjVWimdYP8JovfX1pl01hSBj017yZJJ9/PMxhn umiR9h3UsdQBPLZMzeGR4lO+gTQt9+opyBpUXWNmR3fVx7IA0WOIvtN6g7RrhC3IE+q1 E6GDg3plXJukaO7M5Gn/ws5RRs5feDgVmMeOwkqe1Zb2Uf190rh5wnRMu6Ot0s6ON077 3hq4cRJXwSs3eAShB+RZvC7ySjbkyVDKKFKDtaW87zd11oUjOwrTOeooAMxNHw+aSqtq 0xWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=b9m1nmaWtWBwif+xXJu8UuQzESZbAhj4RM3etQ7FUiM=; b=irDsYEPuozFLZSZdNhbcNr/lex6FnYp69zEm4sxw1pPRCY6Dkp3EWcIxLS561/h7JN vs1CWbILC/qF8eY1js+faHMn/ABlHAltbC7/jcJo4JPP2wHZPdxQtbgfe11oucTq0QMk cWEToTOPXULWLu+V9uf3QMBKWf9ajWWhE1o2+h4AGqQ3yAU0rUkg/caHt4ypkJKuW5g4 /IAtf1aPfxjFIA4qpqFbtBN0Zj017TrWsnsriPZT1fM6K4EXfF7LZckgsKOoerXetpUz reDW6VSqeUC8QwkzycPWOmvuY0TmQDySqK/zA10KikPddV6hqZsSJKhnB05pXWnsuUvz Acfg== X-Gm-Message-State: AMCzsaUN3itNB9voseDqcI3weZOQ070sTOVGRtB+6M0WjIU6kxm3ivpr iDMCHrwpZMB6w2rvTDb4wjg= X-Received: by 10.84.213.9 with SMTP id f9mr6257321pli.76.1509343436987; Sun, 29 Oct 2017 23:03:56 -0700 (PDT) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id f191sm3130794pgc.32.2017.10.29.23.03.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 29 Oct 2017 23:03:55 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Mon, 30 Oct 2017 16:33:48 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v5 5/5] clk: aspeed: Add reset controller Date: Mon, 30 Oct 2017 16:32:50 +1030 Message-Id: <20171030060250.701-6-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171030060250.701-1-joel@jms.id.au> References: <20171030060250.701-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v5: - Add Andrew's Reviewed-by v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 10 ++++ 2 files changed, 91 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index df5bc57a6ee2..d91e86c70e0c 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -275,6 +276,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -316,10 +379,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -327,6 +391,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4a99421d77c8..8e19646d8025 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,4 +39,14 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + #endif