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[209.132.180.67]) by mx.google.com with ESMTP id k8si23893167pgt.29.2017.11.27.23.20.26; Mon, 27 Nov 2017 23:20:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=fail header.i=@gmail.com header.s=20161025 header.b=WdCk+3ho; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752093AbdK1HUY (ORCPT + 28 others); Tue, 28 Nov 2017 02:20:24 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:34458 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751690AbdK1HUW (ORCPT ); Tue, 28 Nov 2017 02:20:22 -0500 Received: by mail-pl0-f65.google.com with SMTP id o17so10139805pli.1; Mon, 27 Nov 2017 23:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=JhFBI1MPf+an05XEAQYvCgTn9As8sDHyGSLy5fYlbm0=; b=WdCk+3hoBaYzhpnkHjvka3Irr3bQzWYUL4As9CO3PYs+uOv9uUXNQURAXZHjD0KsFz vCKOnwP+wGMyZZUGSMBm8h7BSu3Fw59FI5WlhwYBTJmNCV3EnrtrORb9401PvJ37dIAq ENGKEWKCCqVxqpuAedNY+4/s9fzHIDoQcazelLxVkSYHu3Bj+odvB1lOP1yoWNgB0+it W3ZFz6YHJ/a3z2fayYJNRr+M+Sjjlleb22h/ux1/MkUyU1AV+E0eM321Jx84Vtu2lNdS WFEX7mSLC8RbLgMc8ilGJqVJx/DAUVr9pUQT03lK0NoPj7pmKZineCeNsZDnTQO8Veb0 FhxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=JhFBI1MPf+an05XEAQYvCgTn9As8sDHyGSLy5fYlbm0=; b=KrYPE9aGa9ZZbLuLPxRiXmjWtYbjAQ2UiocrCi0lkEgix+lgludtyI8CHJjrSs5q/+ WL5RI0idCXYlh1bzR4Ck/kKsPhek3s8Q1jvbfOT9616HEP5jTmvWdWE7LajrtZawmOmo ECvO0y7t0VnAD4w9mTu3kvqy0RIWmO73wvfXMuxATMb9a0rUWCC7l1C6zZ6/6n/YrPQQ P3VhUbKw9PvATpCD+ph57GAWecGOXWfm+7i9SfthkO5gxJeq1gATNEFhyb2Apm2AibFr V0W4TcrCSATL+FcmKkBYbFSmiWO4I6bHjj/q8t4d03B4ZIiiPwfEQ4bOTsbJdtBiMf6J b8cw== X-Gm-Message-State: AJaThX5t3QvtpzeqalxOTSpW4f2OAa4cstx2KknTRqeDG69glfjy8m3E UMfIzBAd04NYQGh4FBMEkrg= X-Received: by 10.84.141.164 with SMTP id 33mr19826659plv.100.1511853622130; Mon, 27 Nov 2017 23:20:22 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id g127sm41606029pgc.29.2017.11.27.23.20.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 27 Nov 2017 23:20:20 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Tue, 28 Nov 2017 17:50:12 +1030 From: Joel Stanley To: Lee Jones , Michael Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andrew Jeffery , Benjamin Herrenschmidt , Jeremy Kerr , Rick Altherr , Ryan Chen , Arnd Bergmann Subject: [PATCH v6 5/5] clk: aspeed: Add reset controller Date: Tue, 28 Nov 2017 17:49:08 +1030 Message-Id: <20171128071908.12279-6-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171128071908.12279-1-joel@jms.id.au> References: <20171128071908.12279-1-joel@jms.id.au> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There are some resets that are not associated with gates. These are represented by a reset controller. Reviewed-by: Andrew Jeffery Signed-off-by: Joel Stanley --- v5: - Add Andrew's Reviewed-by v3: - Add named initalisers for the reset defines - Add define for ADC --- drivers/clk/clk-aspeed.c | 82 +++++++++++++++++++++++++++++++- include/dt-bindings/clock/aspeed-clock.h | 10 ++++ 2 files changed, 91 insertions(+), 1 deletion(-) -- 2.14.1 diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index b5dc3e298693..f2722be17ede 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -266,6 +267,68 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +static const u8 aspeed_resets[] = { + [ASPEED_RESET_XDMA] = 25, + [ASPEED_RESET_MCTP] = 24, + [ASPEED_RESET_ADC] = 23, + [ASPEED_RESET_JTAG_MASTER] = 22, + [ASPEED_RESET_MIC] = 18, + [ASPEED_RESET_PWM] = 9, + [ASPEED_RESET_PCIVGA] = 8, + [ASPEED_RESET_I2C] = 2, + [ASPEED_RESET_AHB] = 1, +}; + +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0); +} + +static int aspeed_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = BIT(aspeed_resets[id]); + + return regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst); +} + +static int aspeed_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 val, rst = BIT(aspeed_resets[id]); + int ret; + + ret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_reset_ops = { + .assert = aspeed_reset_assert, + .deassert = aspeed_reset_deassert, + .status = aspeed_reset_status, +}; + static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct regmap *map, u8 clock_idx, u8 reset_idx, @@ -307,10 +370,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) { const struct aspeed_clk_soc_data *soc_data; struct device *dev = &pdev->dev; + struct aspeed_reset *ar; struct regmap *map; struct clk_hw *hw; u32 val, rate; - int i; + int i, ret; map = syscon_node_to_regmap(dev->of_node); if (IS_ERR(map)) { @@ -318,6 +382,22 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(map); } + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); + ar->rcdev.ops = &aspeed_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + /* SoC generations share common layouts but have different divisors */ soc_data = of_device_get_match_data(dev); if (!soc_data) { diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 9e170fb9a0da..fe46ab69da5c 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -41,4 +41,14 @@ #define ASPEED_NUM_CLKS 35 +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + #endif