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[209.132.180.67]) by mx.google.com with ESMTP id z11si22398296plo.291.2017.12.26.02.33.19; Tue, 26 Dec 2017 02:33:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E8Vyd/Ir; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751550AbdLZKdO (ORCPT + 28 others); Tue, 26 Dec 2017 05:33:14 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:45164 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751256AbdLZKbR (ORCPT ); Tue, 26 Dec 2017 05:31:17 -0500 Received: by mail-wr0-f194.google.com with SMTP id o15so2113473wrf.12 for ; Tue, 26 Dec 2017 02:31:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=D1s3sKwENSd9qzpa610Hh5biN2gC6aQuFiXmc8tlfXA=; b=E8Vyd/Ir825/gHmNF9hucE2FDTHkNlIL1/ccXQHHtFoBnIvvMduHO5rZwqp1Hv/ZDN x6t+YjOuNtsM7GrOjckf1u0aBoGwvQAEn75tB9gf3Jcy0Jkpg/AUNOO7ltDmYG0lkQgl wB995ISvR7HjShSethmXDi0S6qukG+kAjpkOM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=D1s3sKwENSd9qzpa610Hh5biN2gC6aQuFiXmc8tlfXA=; b=O9ERQ2rzrTE8MEAPvEu0rROudVyEWs7lShopyjhio+bEiBXOH28PbY7J7gyYnjkmvj Y8UlpA39RznAMT/lcZvpnIf/kJ623dyxNmk9sLqCOdVTA6Zk0tZspGBXjHItmJwBTPYm M3oZllT3XhsEhnKJLPb2bVMArfDRMDV+7b5IeNi+q17Amc3xVEz5BdaruK/tVJEenyhE UwkJSiLDfwKItupCNAIm9HAvFNJ5pZ4lKvbFBWJ77tgHyDTmwz7KKC+OnvcJEauzBb7N LO3F11FbbWhB8JQ9wUmDXYhNJtT4FMI7OSAxs9y1no2wdR8nxzoYUWztwA5feilQgF+n vNVA== X-Gm-Message-State: AKGB3mKx7nsn66BfyHQUFvQQan2sG2o3J/6nwj+zdO957hzbA16wSgov g3abgvFQy9mk69rRfC8e4Qh+ST3OLgk= X-Received: by 10.223.151.208 with SMTP id t16mr14233824wrb.200.1514284275687; Tue, 26 Dec 2017 02:31:15 -0800 (PST) Received: from localhost.localdomain ([160.171.216.245]) by smtp.gmail.com with ESMTPSA id l142sm13974036wmb.43.2017.12.26.02.31.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Dec 2017 02:31:15 -0800 (PST) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v4 13/20] crypto: arm64/sha2-ce - yield NEON after every block of input Date: Tue, 26 Dec 2017 10:29:33 +0000 Message-Id: <20171226102940.26908-14-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171226102940.26908-1-ard.biesheuvel@linaro.org> References: <20171226102940.26908-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/sha2-ce-core.S | 37 ++++++++++++++------ 1 file changed, 26 insertions(+), 11 deletions(-) -- 2.11.0 diff --git a/arch/arm64/crypto/sha2-ce-core.S b/arch/arm64/crypto/sha2-ce-core.S index 679c6c002f4f..e955a42345c0 100644 --- a/arch/arm64/crypto/sha2-ce-core.S +++ b/arch/arm64/crypto/sha2-ce-core.S @@ -77,30 +77,36 @@ * int blocks) */ ENTRY(sha2_ce_transform) + frame_push 3 + + mov x19, x0 + mov x20, x1 + mov x21, x2 + /* load round constants */ - adr x8, .Lsha2_rcon +0: adr x8, .Lsha2_rcon ld1 { v0.4s- v3.4s}, [x8], #64 ld1 { v4.4s- v7.4s}, [x8], #64 ld1 { v8.4s-v11.4s}, [x8], #64 ld1 {v12.4s-v15.4s}, [x8] /* load state */ - ld1 {dgav.4s, dgbv.4s}, [x0] + ld1 {dgav.4s, dgbv.4s}, [x19] /* load sha256_ce_state::finalize */ ldr_l w4, sha256_ce_offsetof_finalize, x4 - ldr w4, [x0, x4] + ldr w4, [x19, x4] /* load input */ -0: ld1 {v16.4s-v19.4s}, [x1], #64 - sub w2, w2, #1 +1: ld1 {v16.4s-v19.4s}, [x20], #64 + sub w21, w21, #1 CPU_LE( rev32 v16.16b, v16.16b ) CPU_LE( rev32 v17.16b, v17.16b ) CPU_LE( rev32 v18.16b, v18.16b ) CPU_LE( rev32 v19.16b, v19.16b ) -1: add t0.4s, v16.4s, v0.4s +2: add t0.4s, v16.4s, v0.4s mov dg0v.16b, dgav.16b mov dg1v.16b, dgbv.16b @@ -129,16 +135,24 @@ CPU_LE( rev32 v19.16b, v19.16b ) add dgbv.4s, dgbv.4s, dg1v.4s /* handled all input blocks? */ - cbnz w2, 0b + cbz w21, 3f + + if_will_cond_yield_neon + st1 {dgav.4s, dgbv.4s}, [x19] + do_cond_yield_neon + b 0b + endif_yield_neon + + b 1b /* * Final block: add padding and total bit count. * Skip if the input size was not a round multiple of the block size, * the padding is handled by the C code in that case. */ - cbz x4, 3f +3: cbz x4, 4f ldr_l w4, sha256_ce_offsetof_count, x4 - ldr x4, [x0, x4] + ldr x4, [x19, x4] movi v17.2d, #0 mov x8, #0x80000000 movi v18.2d, #0 @@ -147,9 +161,10 @@ CPU_LE( rev32 v19.16b, v19.16b ) mov x4, #0 mov v19.d[0], xzr mov v19.d[1], x7 - b 1b + b 2b /* store new state */ -3: st1 {dgav.4s, dgbv.4s}, [x0] +4: st1 {dgav.4s, dgbv.4s}, [x19] + frame_pop ret ENDPROC(sha2_ce_transform)