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[209.132.180.67]) by mx.google.com with ESMTP id z64si23003917pfa.207.2017.12.26.02.31.56; Tue, 26 Dec 2017 02:31:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aKK811K4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751418AbdLZKbi (ORCPT + 28 others); Tue, 26 Dec 2017 05:31:38 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:46708 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751383AbdLZKbb (ORCPT ); Tue, 26 Dec 2017 05:31:31 -0500 Received: by mail-wr0-f193.google.com with SMTP id g17so25079022wrd.13 for ; Tue, 26 Dec 2017 02:31:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8lxYshd4t2vNZUmeSImu2s80h0Moipc7qU5+ubILpV0=; b=aKK811K4WFmrqDBve0JVVT/rshB3oUaC6xVtgUjz33HK471OH/RYwsXbjx/PHDqH7Q oAWUJla4KT2xuse/RHFqvN03lVYlSvL5BW2zawvwEP5Hzu57yoH4qXAK04pyiMOFACj1 UZMkCkzqnEh8JqE8NbSDg+gR1f2mr81Aj/8EM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8lxYshd4t2vNZUmeSImu2s80h0Moipc7qU5+ubILpV0=; b=BrHmHRdlSgi3viw6/Yn8yNhiMU5YwU2LLhgzKJOezEIgrHRD/wlAspq0oxTjij5Yli L5bAtoZR5yAvVwWsatAl9tE4dQxRusOTqAjuRd4PIWL6sdPbLTxf+AV7idMPIgN5z3lY SidxzDG+2hsMShj47enbw8ISbaLr1QpiL9Gwl91/7ygoQONYK/GNpXo0QmUAszANJPP1 ls7oychfouSFZwRQlFSNYhpR1+IcgTiSrDxmKD5zGLIU9EuocSoW3yc5STdwuWrhyRN6 rbw6E+WY9b/QdNhfvp7mUO/aH4oCLjQ3SKTWEDCC8FrnX6GHex8Pj5PHDar/0QpUXzpD cZrg== X-Gm-Message-State: AKGB3mIuZbkTxLkHohUuLfPLvktAm/Rtx4bRSVlEnhdo6M5moV501WEx WginO6dj8M5M1ZCVorU8LF6G4fUDVtg= X-Received: by 10.223.164.5 with SMTP id d5mr23462139wra.172.1514284289659; Tue, 26 Dec 2017 02:31:29 -0800 (PST) Received: from localhost.localdomain ([160.171.216.245]) by smtp.gmail.com with ESMTPSA id l142sm13974036wmb.43.2017.12.26.02.31.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Dec 2017 02:31:29 -0800 (PST) From: Ard Biesheuvel To: linux-kernel@vger.kernel.org Cc: Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v4 18/20] crypto: arm64/crc32-ce - yield NEON after every block of input Date: Tue, 26 Dec 2017 10:29:38 +0000 Message-Id: <20171226102940.26908-19-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171226102940.26908-1-ard.biesheuvel@linaro.org> References: <20171226102940.26908-1-ard.biesheuvel@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/crc32-ce-core.S | 40 +++++++++++++++----- 1 file changed, 30 insertions(+), 10 deletions(-) -- 2.11.0 diff --git a/arch/arm64/crypto/crc32-ce-core.S b/arch/arm64/crypto/crc32-ce-core.S index 18f5a8442276..29a601bb810e 100644 --- a/arch/arm64/crypto/crc32-ce-core.S +++ b/arch/arm64/crypto/crc32-ce-core.S @@ -100,9 +100,10 @@ dCONSTANT .req d0 qCONSTANT .req q0 - BUF .req x0 - LEN .req x1 - CRC .req x2 + BUF .req x19 + LEN .req x20 + CRC .req x21 + CONST .req x22 vzr .req v9 @@ -122,7 +123,14 @@ ENTRY(crc32_pmull_le) ENTRY(crc32c_pmull_le) adr x3, .Lcrc32c_constants -0: bic LEN, LEN, #15 +0: frame_push 4, 64 + + mov BUF, x0 + mov LEN, x1 + mov CRC, x2 + mov CONST, x3 + + bic LEN, LEN, #15 ld1 {v1.16b-v4.16b}, [BUF], #0x40 movi vzr.16b, #0 fmov dCONSTANT, CRC @@ -131,7 +139,7 @@ ENTRY(crc32c_pmull_le) cmp LEN, #0x40 b.lt less_64 - ldr qCONSTANT, [x3] + ldr qCONSTANT, [CONST] loop_64: /* 64 bytes Full cache line folding */ sub LEN, LEN, #0x40 @@ -161,10 +169,21 @@ loop_64: /* 64 bytes Full cache line folding */ eor v4.16b, v4.16b, v8.16b cmp LEN, #0x40 - b.ge loop_64 + b.lt less_64 + + if_will_cond_yield_neon + stp q1, q2, [sp, #.Lframe_local_offset] + stp q3, q4, [sp, #.Lframe_local_offset + 32] + do_cond_yield_neon + ldp q1, q2, [sp, #.Lframe_local_offset] + ldp q3, q4, [sp, #.Lframe_local_offset + 32] + ldr qCONSTANT, [CONST] + movi vzr.16b, #0 + endif_yield_neon + b loop_64 less_64: /* Folding cache line into 128bit */ - ldr qCONSTANT, [x3, #16] + ldr qCONSTANT, [CONST, #16] pmull2 v5.1q, v1.2d, vCONSTANT.2d pmull v1.1q, v1.1d, vCONSTANT.1d @@ -203,8 +222,8 @@ fold_64: eor v1.16b, v1.16b, v2.16b /* final 32-bit fold */ - ldr dCONSTANT, [x3, #32] - ldr d3, [x3, #40] + ldr dCONSTANT, [CONST, #32] + ldr d3, [CONST, #40] ext v2.16b, v1.16b, vzr.16b, #4 and v1.16b, v1.16b, v3.16b @@ -212,7 +231,7 @@ fold_64: eor v1.16b, v1.16b, v2.16b /* Finish up with the bit-reversed barrett reduction 64 ==> 32 bits */ - ldr qCONSTANT, [x3, #48] + ldr qCONSTANT, [CONST, #48] and v2.16b, v1.16b, v3.16b ext v2.16b, vzr.16b, v2.16b, #8 @@ -222,6 +241,7 @@ fold_64: eor v1.16b, v1.16b, v2.16b mov w0, v1.s[1] + frame_pop ret ENDPROC(crc32_pmull_le) ENDPROC(crc32c_pmull_le)