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[209.132.180.67]) by mx.google.com with ESMTP id 33-v6si2776255plu.508.2018.01.31.10.15.02; Wed, 31 Jan 2018 10:15:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=YwFEPemc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754030AbeAaSO3 (ORCPT + 27 others); Wed, 31 Jan 2018 13:14:29 -0500 Received: from mail-wr0-f196.google.com ([209.85.128.196]:39170 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753298AbeAaSJy (ORCPT ); Wed, 31 Jan 2018 13:09:54 -0500 Received: by mail-wr0-f196.google.com with SMTP id f6so14388304wra.6 for ; Wed, 31 Jan 2018 10:09:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XoCwyv3z7MI/oYAqi2dpM7HJlI5GXUwayYtCQqMMLwE=; b=YwFEPemcnVscz36PXu16HOhTSp57QalI1ewgSQ7mCWpSbG8qeNhK2FTHs/hHkLOqfF q9I1ZuSw+wlY/zKJvIIKm8NLnbRJ8akCSUBH1qQZ6P5q+syLergKiGgino8YAV1OOusl 1Uqax4hMw80nb/meahV/LG5ajINZqPTMPHhTd5n/1JjKOjUhJq2BONbP08QDvAIEVW7u 1iC6Jxrx7k+1J5l2nm2mmHd6Cqi9gAnRclWvFVBkgOOSUdNnrkl+uD50+c4fFlGkgoV0 IwG31l9Geqr8UivTgCZAuaEJ78CZUL+huMz/5S43KXB4+EbIvh8fOH12mwc0bU1Vu1kp 723g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XoCwyv3z7MI/oYAqi2dpM7HJlI5GXUwayYtCQqMMLwE=; b=PpnyOnWd1kaxE61lSV5/pthZYRo9H/yqT6tZqsuxC+MzYzIp0Pq6fWdF/+lMvY1WnX NpTBV/7N5/WC2KMP59cld9miEIcCrF7/8p+V6B7ICpbd77SPKi5uag7E3CWUYMn6ucJ1 bt9ryTJks/HKzniJjCAnwFYG5/dow4y5KrdckRkOurk9nBxgRmPPNIhukR9cfSV2Pbhd zCmHI1wM4D6ayl0W82sVodUU21cUZCEARRnCnOuc29FPGL4owaf8wTF637v8L2OmygLj WdabdaxqHnfcpv/yDuh1xS9JOTskSEYJsL6Qg73a1TcGl50uLnx7WYq236+s3wW3kA0G +ngA== X-Gm-Message-State: AKwxytcQ2CeqDVgwEZ0NAFVeByLqbLReGac7YKSKojIxPWB5DGnuRbL/ 3SMQNrfxgM0bl4XcvmTZYysgzA== X-Received: by 10.223.173.119 with SMTP id p110mr16001416wrc.69.1517422193522; Wed, 31 Jan 2018 10:09:53 -0800 (PST) Received: from boomer.baylibre.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id f8sm341977wmc.3.2018.01.31.10.09.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 Jan 2018 10:09:53 -0800 (PST) From: Jerome Brunet To: Neil Armstrong , Kevin Hilman Cc: Jerome Brunet , Stephen Boyd , Michael Turquette , Carlo Caione , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/19] clk: meson: remove obsolete comments Date: Wed, 31 Jan 2018 19:09:30 +0100 Message-Id: <20180131180945.18025-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180131180945.18025-1-jbrunet@baylibre.com> References: <20180131180945.18025-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Over time things changes in CCF and issues have been fixed in meson controllers. Now, clk81 is decently modeled by read-only PLLs, a mux, a divider and a gate. We can remove the FIXME comments related to clk81. Also remove the comment about devm_clk_hw_register, as there is apparently nothing wrong with it. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg.c | 5 ----- drivers/clk/meson/gxbb.c | 6 ------ drivers/clk/meson/meson8b.c | 1 - 3 files changed, 12 deletions(-) -- 2.14.3 diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 81565b025b70..f84927e76f88 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -411,11 +411,6 @@ static struct meson_clk_mpll axg_mpll3 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index e6adab49c0ba..6609024eee00 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -575,12 +575,6 @@ static struct meson_clk_mpll gxbb_mpll2 = { }, }; -/* - * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers - * and should be modeled with their respective PLLs via the forthcoming - * coordinated clock rates feature - */ - static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 }; static const char * const clk81_parent_names[] = { "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4", diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index ffadad27375e..db017c29a84c 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -849,7 +849,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) if (!meson8b_hw_onecell_data.hws[i]) continue; - /* FIXME convert to devm_clk_register */ ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[i]); if (ret) return ret;