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[209.132.180.67]) by mx.google.com with ESMTP id p29si948221pgd.392.2018.03.24.06.33.19; Sat, 24 Mar 2018 06:33:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UV2fGZ9y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752305AbeCXNdQ (ORCPT + 28 others); Sat, 24 Mar 2018 09:33:16 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:38786 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752273AbeCXNdN (ORCPT ); Sat, 24 Mar 2018 09:33:13 -0400 Received: by mail-pl0-f67.google.com with SMTP id m22-v6so9134950pls.5 for ; Sat, 24 Mar 2018 06:33:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LnvVZPRURX9Gme+QX470aYmHcqJ19kBDdz1oGQSy80Q=; b=UV2fGZ9ykD/HPy9CiCgsoFpj97UpazIoJiHUgquSvI6nJnGXHlqYQdctRMpFCoCGaA Y+r38sNKFs0ml326+tDKBc7bLDMAnuyRk5jmocebdhk9bnMw3QJtwOEdy8mpPKvK0mRx VZmV/pfpmLFwscGBNRizFPUiTELkerZt3CcMo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LnvVZPRURX9Gme+QX470aYmHcqJ19kBDdz1oGQSy80Q=; b=SzAzJcPC9ytmliOnDX3bTlM5dkAafJuNpuZs1H1zDf4OLBHKZoImyo8N+kWSPtoxfQ AU0KMtVDdTJjL0gWxz5FOf4n6ihZz2VHZOlbxOJvo6pRKWI49WMgxGeL81umjh4N9aSr 51wUjBywTFzDkqX90WbMNCWRT9CLXq7IQUUEodU9OZcDvSLDGLYZppOqBoX7X8MrXJ/K /e2Qomh3nhwLLXBTKr5OcIO0sRFpA8jYiF62W2ZINKacSp6II1FnhaucsiOH4Lj/CNZr mM6RKLgJSzvEdlCxcWyy7ZCv05vsPKjNZWO5n8cVYLc3+juikkQiBP4Gvr04X0CCGmjx nVHQ== X-Gm-Message-State: AElRT7EXFws1GgTQrkBcKODzTHo/BcgJj/yl8/Jt09uwcpxKl3VWzL5u aSb+V/qBlAZIRYu99T/gzeFw X-Received: by 2002:a17:902:6884:: with SMTP id i4-v6mr34233483plk.259.1521898393326; Sat, 24 Mar 2018 06:33:13 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7401:11e6:b12d:f551:4edc:7f21]) by smtp.gmail.com with ESMTPSA id a76sm4133980pfc.97.2018.03.24.06.33.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Mar 2018 06:33:12 -0700 (PDT) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org, mark.rutland@arm.com Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, davem@davemloft.net, mchehab@kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, viresh.kumar@linaro.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH v6 02/11] arm64: dts: actions: Source CMU clock for UART5 Date: Sat, 24 Mar 2018 19:01:50 +0530 Message-Id: <20180324133159.4824-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> References: <20180324133159.4824-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Remove fixed clock and source CMU (Clock Management Unit) clock for UART5 driver in Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/actions/s900-bubblegum-96.dts | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) -- 2.14.1 diff --git a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts index 21ca80f9941c..ff043c961d75 100644 --- a/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts +++ b/arch/arm64/boot/dts/actions/s900-bubblegum-96.dts @@ -24,12 +24,6 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; - - uart5_clk: uart5-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &timer { @@ -38,5 +32,5 @@ &uart5 { status = "okay"; - clocks = <&uart5_clk>; + clocks = <&cmu CLK_UART5>; };