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[209.132.180.67]) by mx.google.com with ESMTP id j12-v6si5141151pgv.412.2018.05.17.19.32.25; Thu, 17 May 2018 19:32:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BVt5VRYz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752219AbeERCcW (ORCPT + 29 others); Thu, 17 May 2018 22:32:22 -0400 Received: from mail-pl0-f66.google.com ([209.85.160.66]:46496 "EHLO mail-pl0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752180AbeERCcR (ORCPT ); Thu, 17 May 2018 22:32:17 -0400 Received: by mail-pl0-f66.google.com with SMTP id 30-v6so3656909pld.13 for ; Thu, 17 May 2018 19:32:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=k2h++0P+vSVJgWR3WEQ/CkYqyxumbwRoxnODPEzPaMc=; b=BVt5VRYzofvQFucl/sYY7gvPPMCCymT5DmSjWr6vWFZ1gAnct0z1Ia6V4cra00qn47 d57k1jiJYMJbmoFlvKz1p25yiARha3r2i7NfjpjFYKHtJLnQt45J4Mw3iyLA1QsTxnik hT14s7xMFCCBc3ZKuVQMcWrR3qT9EZt6sq8BI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=k2h++0P+vSVJgWR3WEQ/CkYqyxumbwRoxnODPEzPaMc=; b=Y4AHRsbHKX3LA2696gnri33ulPM+n6jRT0ffferXaSJ45MwsfcNKIxppI8Y/KdGXuJ VkDyWVckKAK5SWPoYJB5QFaYm2C2hWQreyIAKV61NX0unP37qZitZNy3xsDjxZfYIqZO kSaPGv3IkYSEAhstJ0KiI+sa/zTtmBt9omAnqFXCoWPLmlydqRg3pe9vxtZnkewUcHqT jvEL+GOBB/BjKrehqWVs2OHYAOlAwDxGRjVNOQsF5ljyge9UherVSFnv2RkAcx4xx5YO S/4MbcnYWgR48vMbcGbXX6NECpPf/pI44DCu88m2zSptqX1vmw291LgAQOGgP10mDSFC VgDw== X-Gm-Message-State: ALKqPwfoBX4qp9neBKZXA5lZUALdfRBnF3krVxboHjGeexT7Eegjcy6S lhufRCldbPioYmnG904TOKCk X-Received: by 2002:a17:902:7402:: with SMTP id g2-v6mr7841121pll.246.1526610737035; Thu, 17 May 2018 19:32:17 -0700 (PDT) Received: from localhost.localdomain ([2405:204:724c:fe7b:a56e:eddc:eaff:36b1]) by smtp.gmail.com with ESMTPSA id z15-v6sm8671085pgr.55.2018.05.17.19.32.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 May 2018 19:32:16 -0700 (PDT) From: Manivannan Sadhasivam To: linus.walleij@linaro.org, robh+dt@kernel.org, afaerber@suse.de Cc: liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, andy.shevchenko@gmail.com, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, Manivannan Sadhasivam Subject: [PATCH 1/5] dt-bindings: pinctrl: Add gpio bindings for Actions S900 SoC Date: Fri, 18 May 2018 08:00:52 +0530 Message-Id: <20180518023056.7869-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180518023056.7869-1-manivannan.sadhasivam@linaro.org> References: <20180518023056.7869-1-manivannan.sadhasivam@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add gpio bindings for Actions Semi S900 SoC. Signed-off-by: Manivannan Sadhasivam --- .../devicetree/bindings/pinctrl/actions,s900-pinctrl.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.14.1 diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt index fb87c7d74f2e..300a50783aab 100644 --- a/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt @@ -8,6 +8,15 @@ Required Properties: - reg: Should contain the register base address and size of the pin controller. - clocks: phandle of the clock feeding the pin controller +- gpio-controller: Marks the device node as a GPIO controller. +- #gpio-cells: Should be two. The first cell is the gpio pin number + and the second cell is used for optional parameters. +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells: Specifies the number of cells needed to encode an + interrupt. Shall be set to 2. The first cell + defines the interrupt number, the second encodes + the trigger flags described in + bindings/interrupt-controller/interrupts.txt Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the @@ -164,6 +173,10 @@ Example: compatible = "actions,s900-pinctrl"; reg = <0x0 0xe01b0000 0x0 0x1000>; clocks = <&cmu CLK_GPIO>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; uart2-default: uart2-default { pinmux {