From patchwork Tue Jun 19 19:42:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 139246 Delivered-To: patch@linaro.org Received: by 2002:a2e:970d:0:0:0:0:0 with SMTP id r13-v6csp5612827lji; Tue, 19 Jun 2018 12:44:05 -0700 (PDT) X-Google-Smtp-Source: ADUXVKJAz3NL1bI4/lZ8R62Fn4/Xk+JXq4SQ8F/u37ACp4T3Zn7qzSVZwctzhjqm001pCQPcgYyJ X-Received: by 2002:a63:6ecb:: with SMTP id j194-v6mr16224901pgc.158.1529437444807; Tue, 19 Jun 2018 12:44:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1529437444; cv=none; d=google.com; s=arc-20160816; b=A9cIGoTb0CnTmN4ALNYp/1eBX7ldYCAZGE24ziSlthVbkTrlQJ2cU49XoqK0+8KgQv aGSCc7ULjgb9D0tsHRGSGL6SnSb+OStl3kT3IaNhZh2F28kgwx1fXxo9szrxyKVhK5ZC my6+OzByJ9biUeJ9YGatgmkAVBLpY59fMjpMwJPwkltoeSOQYUcSAweox1HiNR+6rTcQ +qrs1cEqdqxFV0BjpwiBjABTKLbepwj18bOsM8flRt1Y2j8LiM8KNeVymcpshazy90m/ 2Ux3QBsyBTu8Py9P75xCPi6pHfQYuhRqV2PtIYBcqDYsLcjM9Co45TQcd+8zzJgjsBQH d/uQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=modL2jG/kiKtgtGIGFuxTlZlYEuOikqKeAhaf1/O05s=; b=zEPmjqE/Vo4F4/EV3QHEwrDdQlB3CVS389BQAiv9PeuHsABlFhHlcj0txo7Rg9xsOa NYxS+zbww0cr9iIRJ+KPM4kESIFogozn+DGrm3gdPpGlY25DZYhVfg3aiKKcGy198Fue 3eNgMmziheAfHy/1ZfptGdmVEqO+VtcWkv1D8zbFO3zRAI6UynLq4FJSRKl7M5M2y5jO 4a06iibnNQ6QNnJkZhRrZIM0zLb6evHDXBfDa0xRHR8D5Nc5wkz6y93wRu+dXi/eQMfN n5awee75Ad1pG7tH+2oJEBb+KnCQ/qTOGmoHmdTb2e6YPqT5WjmDSnIS3Pp7NqPwJem2 Hi9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RrDTFB6y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c12-v6si450098pll.75.2018.06.19.12.44.04; Tue, 19 Jun 2018 12:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RrDTFB6y; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030633AbeFSToA (ORCPT + 30 others); Tue, 19 Jun 2018 15:44:00 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:24551 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030433AbeFSTnw (ORCPT ); Tue, 19 Jun 2018 15:43:52 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id w5JJgsYh022473; Tue, 19 Jun 2018 14:42:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1529437374; bh=modL2jG/kiKtgtGIGFuxTlZlYEuOikqKeAhaf1/O05s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RrDTFB6ylp7JmhpNPE1fZvBG5jqPqAMGItuvkCVdcd9PHXWCZ3GETPDSjvDBiNt2v gTKcvejN/+JkR1gzb0SDFZNSSVJHisW0gEp857ZHzKvIt7Fsvyrb+RfWjPcb21SChT cMs/VWAvIFEyNUfi1VGbblegv7nZsLN4Va4cSLxM= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJgs9p023379; Tue, 19 Jun 2018 14:42:54 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 19 Jun 2018 14:42:53 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 19 Jun 2018 14:42:53 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5JJgrw9016519; Tue, 19 Jun 2018 14:42:53 -0500 From: Nishanth Menon To: Will Deacon , Catalin Marinas , Mark Rutland , Rob Herring CC: Tony Lindgren , Russell King , Santosh Shilimkar , , , , Nishanth Menon , Tero Kristo , Sekhar Nori , Olof Johansson , Arnd Bergmann , Sudeep Holla Subject: [PATCH 3/5] arm64: dts: ti: Add Support for AM654 SoC Date: Tue, 19 Jun 2018 14:42:51 -0500 Message-ID: <20180619194253.27288-4-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180619194253.27288-1-nm@ti.com> References: <20180619194253.27288-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The AM654 SoC is a lead device of the K3 Multicore SoC architecture platform, targeted for broad market and industrial control with aim to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Quad ARMv8 A53 cores split over two clusters * GICv3 compliant GIC500 * Configurable L3 Cache and IO-coherent architecture * Dual lock-step capable R5F uC for safety-critical applications * High data throughput capable distributed DMA architecture under NAVSS * Three Gigabit Industrial Communication Subsystems (ICSSG), each with dual PRUs and dual RTUs * Hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL * Centralized System Controller for Security, Power, and Resource management. * Dual ADCSS, eQEP/eCAP, eHRPWM, dual CAN-FD * Flash subsystem with OSPI and Hyperbus interfaces * Multimedia capability with CAL, DSS7-UL, SGX544, McASP * Peripheral connectivity including USB3, PCIE, MMC/SD, GPMC, I2C, SPI, GPIO See AM65x Technical Reference Manual (SPRUID7, April 2018) for further details: http://www.ti.com/lit/pdf/spruid7 NOTE: 1. AM654 is the first of the device variants, hence we introduce a generic am65.dtsi. 2. We indicate the proper bus topology, the ranges are elaborated in each bus segment instead of using the top level ranges to make sure that peripherals in each segment use the address space accurately. 3. Peripherals in each bus segment is maintained in a separate dtsi allowing for reuse in different bus segment representation from a different core such as R5. This is also the reason for maintaining a 1-1 address map in the ranges. 4. Cache descriptions follow the ARM64 standard description. Further tweaks may be necessary as we introduce more complex devices, but can be introduced in context of the device introduction. Signed-off-by: Benjamin Fair Signed-off-by: Nishanth Menon --- Changes since RFC: * Bus topology representation * Device nodes underneath a bus segment moved to seperate dtsi (allowing reuse where applicable) * Ranges used in the bus segments * Processor level nodes moved to the root node * SoC node dropped. * Default for device nodes is "enabled" instead of explicitly enabling them in board dts. * UART patches are spun off into a different series to prevent maintainer tree level conflicts. (wakeup and mcu domain peripherals to be introduced there) * Few addresses had uppercase hexadecimal values, replaced with standard lowercase hex values * Commit message updates * Kconfig was spun out as seperate patch RFC: https://patchwork.kernel.org/patch/10447719/ , https://patchwork.kernel.org/patch/10453659/ MAINTAINERS | 1 + arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 31 +++++++++ arch/arm64/boot/dts/ti/k3-am65.dtsi | 87 +++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am654.dtsi | 115 +++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am65-main.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am65.dtsi create mode 100644 arch/arm64/boot/dts/ti/k3-am654.dtsi -- 2.15.1 diff --git a/MAINTAINERS b/MAINTAINERS index fbd93eee41ae..6785ceaf5b0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2093,6 +2093,7 @@ M: Nishanth Menon L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Supported F: Documentation/devicetree/bindings/arm/ti/k3.txt +F: arch/arm64/boot/dts/ti/k3-* ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE M: Santosh Shilimkar diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi new file mode 100644 index 000000000000..2409344df4fa --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family Main Domain peripherals + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +&cbass_main { + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x01800000 0x10000>, /* GICD */ + <0x01880000 0x90000>; /* GICR */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = ; + + gic_its: gic-its@18200000 { + compatible = "arm,gic-v3-its"; + reg = <0x01820000 0x10000>; + msi-controller; + #msi-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi new file mode 100644 index 000000000000..8c0f78332157 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC Family + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include +#include + +/ { + model = "Texas Instruments K3 AM654 SoC"; + compatible = "ti,am654"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = , /* cntpsirq */ + , /* cntpnsirq */ + , /* cntvirq */ + ; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,armv8-pmuv3"; + /* Recommendation from GIC500 TRM Table A.3 */ + interrupts = ; + }; + + cbass_main: cbass@100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00100000 0x00 0x00100000 0x00020000>, /* ctrl mmr */ + <0x00600000 0x00 0x00600000 0x00001100>, /* GPIO */ + <0x00900000 0x00 0x00900000 0x00012000>, /* serdes */ + <0x01000000 0x00 0x01000000 0x0af02400>, /* Most peripherals */ + <0x30800000 0x00 0x30800000 0x0bc00000>, /* MAIN NAVSS */ + /* MCUSS Range */ + <0x28380000 0x00 0x28380000 0x03880000>, + <0x40200000 0x00 0x40200000 0x00900100>, + <0x42040000 0x00 0x42040000 0x03ac2400>, + <0x45100000 0x00 0x45100000 0x00c24000>, + <0x46000000 0x00 0x46000000 0x00200000>, + <0x47000000 0x00 0x47000000 0x00068400>; + + cbass_mcu: cbass@28380000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x28380000 0x28380000 0x03880000>, /* MCU NAVSS*/ + <0x40200000 0x40200000 0x00900100>, /* First peripheral window */ + <0x42040000 0x42040000 0x03ac2400>, /* WKUP */ + <0x45100000 0x45100000 0x00c24000>, /* MMRs, remaining NAVSS */ + <0x46000000 0x46000000 0x00200000>, /* CPSW */ + <0x47000000 0x47000000 0x00068400>; /* OSPI space 1 */ + + cbass_wakeup: cbass@42040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* WKUP Basic peripherals */ + ranges = <0x42040000 0x42040000 0x03ac2400>; + }; + }; + }; +}; + +/* Now include the peripherals for each bus segments */ +#include "k3-am65-main.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am654.dtsi b/arch/arm64/boot/dts/ti/k3-am654.dtsi new file mode 100644 index 000000000000..2affa6f6617e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654.dtsi @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM6 SoC family in Quad core configuration + * + * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include "k3-am65.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1: cluster1 { + core0 { + cpu = <&cpu2>; + }; + + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&L2_1>; + }; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + L2_1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&msmc_l3>; + }; + + msmc_l3: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + }; +};