From patchwork Mon Jul 16 15:36:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 142039 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp2569549ljj; Mon, 16 Jul 2018 08:38:31 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfUXgveerJKYkFeqJsGxKHngrpi/gNJKqGg7YPyp3RU8geBrmrTIwBTRgXS3ulUop9FcWM6 X-Received: by 2002:a63:5c7:: with SMTP id 190-v6mr15634614pgf.385.1531755511220; Mon, 16 Jul 2018 08:38:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531755511; cv=none; d=google.com; s=arc-20160816; b=xE6rVOOESZGzW2pqYnUYs1lM/XusDq1y3ZHcv1Ww/QwoYb3aOwkei/6IWgk2FczW0A zkp8PXWIPfoqVbDuEaDSEcryUF7eqo4IqSgPjtnpnWXG1c6X6bPA/o1MAPv4vlApei0t deLbeRJRmkv4h/aLTedVG9JeJYfGS9buWXAusFIYRStBmE1fDTDpOgGzjq2dzJPZTej9 wBRLB966n7/yl9jjN/62gVntRiLUDFMfi7BBr1WoKyg+f000nYApDP1/wSbuapcXltDI gaB46/bBmEQqsiEMHML23gRS5xYEOfJu39TZvjc1BqYYQzLEfZ9EwVtG+hccR1iJ8+CM lwjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=RydeVn7HLC1NSYoqB0O/U3s9982d2tocwGiI60kFjrc=; b=TRo/S+I0/qC9H7HYEFOfyGP/pag++poCDo2ZrsipS0SO7llGG40Ny/8pr5z1sRQ3xi cyTPCQpLHSn/HDmVj/6og5PtzLoAEpZ1LzRxFuY4Xy8Qfh9n5bsyMv1k9R2PVOdYR6yx vQ90WddWNOaAyvcHXffHqf+wNEqHg9SA6Y3suY5FG1kbJfa3RB8l5RvNTTtFVObDisY7 WvB361qc/Mu3kG2s3Fn3PaeavOOFwPh+0oVc02bit4931iXtgKBgDZmQuymm1HByJdtb jSpJNqZCzISWHxIK7GgRjnkOu2VLgDLPDkxZZKXw69mYk/5U8rEB066EXUXfE6G1PrFJ xusg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m3-v6si27402922pgr.108.2018.07.16.08.38.30; Mon, 16 Jul 2018 08:38:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730795AbeGPQFX (ORCPT + 31 others); Mon, 16 Jul 2018 12:05:23 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:9626 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727715AbeGPQFW (ORCPT ); Mon, 16 Jul 2018 12:05:22 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 128E92D81D973; Mon, 16 Jul 2018 23:37:09 +0800 (CST) Received: from S00293818-DELL1.huawei.com (10.202.226.54) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.382.0; Mon, 16 Jul 2018 23:37:04 +0800 From: Salil Mehta To: CC: , , , , , , , Huazhong Tan Subject: [PATCH net-next 1/9] net: hns3: Modify the order of initializing command queue register Date: Mon, 16 Jul 2018 16:36:19 +0100 Message-ID: <20180716153627.476-2-salil.mehta@huawei.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180716153627.476-1-salil.mehta@huawei.com> References: <20180716153627.476-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.226.54] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Huazhong Tan According to hardware's description, the head pointer register should be written before the tail pointer register while doing command queue initialization. Signed-off-by: Huazhong Tan Signed-off-by: Peng Li Signed-off-by: Salil Mehta --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c index eca4b23..cf40afc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c @@ -119,8 +119,8 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring) hclge_write_dev(hw, HCLGE_NIC_CSQ_DEPTH_REG, (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) | HCLGE_NIC_CMQ_ENABLE); - hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0); hclge_write_dev(hw, HCLGE_NIC_CSQ_HEAD_REG, 0); + hclge_write_dev(hw, HCLGE_NIC_CSQ_TAIL_REG, 0); } else { hclge_write_dev(hw, HCLGE_NIC_CRQ_BASEADDR_L_REG, lower_32_bits(dma)); @@ -129,8 +129,8 @@ static void hclge_cmd_config_regs(struct hclge_cmq_ring *ring) hclge_write_dev(hw, HCLGE_NIC_CRQ_DEPTH_REG, (ring->desc_num >> HCLGE_NIC_CMQ_DESC_NUM_S) | HCLGE_NIC_CMQ_ENABLE); - hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0); hclge_write_dev(hw, HCLGE_NIC_CRQ_HEAD_REG, 0); + hclge_write_dev(hw, HCLGE_NIC_CRQ_TAIL_REG, 0); } }