From patchwork Wed Dec 19 12:42:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 154263 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp4890856ljp; Wed, 19 Dec 2018 04:43:26 -0800 (PST) X-Google-Smtp-Source: AFSGD/XCujvzNaM2fq/IUubonpeJTWNqJGu88sSYwKASLzO8WEgW8XfjV6LYD9++5T09h+0B8l6A X-Received: by 2002:a17:902:9f93:: with SMTP id g19mr19818841plq.195.1545223406692; Wed, 19 Dec 2018 04:43:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1545223406; cv=none; d=google.com; s=arc-20160816; b=aVTHmNFQ8PLdvXHjiDfBY7kvrUEmesCWhoh8OhT7/IVVAayFTtJGZyrZfeUDLhMOaP +fZd/Ayp8vinFgWpUM25qY3YTeUwS6ePDgg3cujve6XKFZC75fLcVHq428bN1UOEyS5c 9c1yOEBDtRRP05UWQG14J8rTWwpLQJowmIPS74Y+XmdFNbebCuZk8g0aYjcAJKV8TQX0 Ard8B1dlqELH3mH4BT1O4DnSacdSgzN4Jzs950lntvcQO9VJftU89k0Akp67KcV4V2nW guGhu4AM3FAN1KmrtncNf1Q1etG6W9nsV2Xh88dzp7yeoZeSC3GzG5+hDAsdhjhe4yjv epqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=s8YQTAlDMbSOqhf4u+bKfrqy75XWX+0He0qtHas8k58=; b=DmVO1d/R1zK4w92WcyNWcMta22SnkCNhZBmB0j3ShNEftevPw3rjkLZHdoHxX5Eegn MPX4GbQmQZtDrku2jsEJATHSrhnnE3Dai/XjDKSVflwkeYCIhzekVVEjoyHwPtSQH9Gj 8QMts2qCTkZQLSDF+NPad1Qnymv89PgDxsGuMQonGFZvVNFMO4AZ13MYF/mM8d898ZEe DpAb8mdoNQkTp2Vu5R6fh+zuMHiabcNgMhKKADZoz7KtEzWo2UnZtEVZKPinWs+/Mauj +iGlO3TaxnsisVvmHAK80d7wtoWla58uuF5wntFZJqkoLIRgtt1IDACohHrTOA+rJs5g 8G7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B4XRHDBL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h9si16208598pgb.319.2018.12.19.04.43.26; Wed, 19 Dec 2018 04:43:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=B4XRHDBL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729892AbeLSMnZ (ORCPT + 31 others); Wed, 19 Dec 2018 07:43:25 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:38698 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729858AbeLSMnT (ORCPT ); Wed, 19 Dec 2018 07:43:19 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wBJCgqC6128202; Wed, 19 Dec 2018 06:42:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1545223372; bh=s8YQTAlDMbSOqhf4u+bKfrqy75XWX+0He0qtHas8k58=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=B4XRHDBLQXnhVbGq2D9BiU8thbQgCyVJS6yPQajIZlBEoWJgiTFVRRD+Sy0Xs0ZVN 5nUoPRPhswPYbt9oEIPgm+mHerJg+MWAUKNHZMNlgJVtssC80GmuZSaeDEGRZ+Sv5v o+5w1aHHwZmm8g1QwMRkDM/XVy5i5JCv9RTinX/4= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wBJCgp9j041051 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 19 Dec 2018 06:42:52 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 19 Dec 2018 06:42:51 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 19 Dec 2018 06:42:51 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wBJCgNZr003940; Wed, 19 Dec 2018 06:42:48 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi , Gustavo Pimentel , Marc Zyngier CC: Bjorn Helgaas , Jingoo Han , , , , Subject: [PATCH 08/10] PCI: keystone: Use Keystone specific msi_irq_chip Date: Wed, 19 Dec 2018 18:12:05 +0530 Message-ID: <20181219124207.13479-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181219124207.13479-1-kishon@ti.com> References: <20181219124207.13479-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use Keystone specific msi_irq_chip to configure the MSI controller logic in the PCIe keystone wrapper instead of using the default Designware msi_irq chip (dw_pci_msi_bottom_irq_chip) with callback functions for configuring the Keystone MSI controller. This will help to remove Keystone specific callback functions added in dw_pcie_host_ops. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 96 +++++++++++++++++------ 1 file changed, 72 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 05b2bd613c68..420d30ce11f4 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -104,14 +104,6 @@ struct keystone_pcie { struct resource app; }; -static phys_addr_t ks_pcie_get_msi_addr(struct pcie_port *pp) -{ - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); - - return ks_pcie->app.start + MSI_IRQ; -} - static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) { return readl(ks_pcie->va_app_base + offset); @@ -123,11 +115,14 @@ static void ks_pcie_app_writel(struct keystone_pcie *ks_pcie, u32 offset, writel(val, ks_pcie->va_app_base + offset); } -static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) +static void ks_pcie_msi_irq_ack(struct irq_data *data) { - u32 reg_offset, bit_pos; + struct pcie_port *pp = irq_data_get_irq_chip_data(data); struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; struct dw_pcie *pci; + u32 reg_offset; + u32 bit_pos; pci = to_dw_pcie_from_pp(pp); ks_pcie = to_keystone_pcie(pci); @@ -140,34 +135,91 @@ static void ks_pcie_msi_irq_ack(int irq, struct pcie_port *pp) ks_pcie_app_writel(ks_pcie, IRQ_EOI, reg_offset + MSI_IRQ_OFFSET); } -static void ks_pcie_msi_set_irq(struct pcie_port *pp, int irq) +static void ks_pcie_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + struct dw_pcie *pci; + u64 msi_target; + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); + + msi_target = ks_pcie->app.start + MSI_IRQ; + msg->address_lo = lower_32_bits(msi_target); + msg->address_hi = upper_32_bits(msi_target); + msg->data = data->hwirq; + + dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n", + (int)data->hwirq, msg->address_hi, msg->address_lo); +} + +static int ks_pcie_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -EINVAL; +} + +static void ks_pcie_msi_mask(struct irq_data *data) +{ + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } -static void ks_pcie_msi_clear_irq(struct pcie_port *pp, int irq) +static void ks_pcie_msi_unmask(struct irq_data *data) { - u32 reg_offset, bit_pos; - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); - struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct pcie_port *pp = irq_data_get_irq_chip_data(data); + struct keystone_pcie *ks_pcie; + u32 irq = data->hwirq; + struct dw_pcie *pci; + unsigned long flags; + u32 reg_offset; + u32 bit_pos; + + raw_spin_lock_irqsave(&pp->lock, flags); + + pci = to_dw_pcie_from_pp(pp); + ks_pcie = to_keystone_pcie(pci); reg_offset = irq % 8; bit_pos = irq >> 3; - ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_CLR(reg_offset), + ks_pcie_app_writel(ks_pcie, MSI_IRQ_ENABLE_SET(reg_offset), BIT(bit_pos)); + + raw_spin_unlock_irqrestore(&pp->lock, flags); } +static struct irq_chip ks_pcie_msi_irq_chip = { + .name = "KEYSTONE-PCI-MSI", + .irq_ack = ks_pcie_msi_irq_ack, + .irq_compose_msi_msg = ks_pcie_compose_msi_msg, + .irq_set_affinity = ks_pcie_msi_set_affinity, + .irq_mask = ks_pcie_msi_mask, + .irq_unmask = ks_pcie_msi_unmask, +}; + static int ks_pcie_msi_host_init(struct pcie_port *pp) { + pp->msi_irq_chip = &ks_pcie_msi_irq_chip; return dw_pcie_allocate_domains(pp); } @@ -768,11 +820,7 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .rd_other_conf = ks_pcie_rd_other_conf, .wr_other_conf = ks_pcie_wr_other_conf, .host_init = ks_pcie_host_init, - .msi_set_irq = ks_pcie_msi_set_irq, - .msi_clear_irq = ks_pcie_msi_clear_irq, - .get_msi_addr = ks_pcie_get_msi_addr, .msi_host_init = ks_pcie_msi_host_init, - .msi_irq_ack = ks_pcie_msi_irq_ack, .scan_bus = ks_pcie_v3_65_scan_bus, };