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[209.132.180.67]) by mx.google.com with ESMTP id j14si4875956pfe.152.2019.02.13.05.27.49; Wed, 13 Feb 2019 05:27:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=YuUBJZma; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390953AbfBMN1r (ORCPT + 31 others); Wed, 13 Feb 2019 08:27:47 -0500 Received: from lelv0143.ext.ti.com ([198.47.23.248]:38438 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390916AbfBMN1o (ORCPT ); Wed, 13 Feb 2019 08:27:44 -0500 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x1DDRVQi071631; Wed, 13 Feb 2019 07:27:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1550064451; bh=7MdHPJ7rWOh896bss+DBXdVKPNNaFRcm80DCZwUWhMw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YuUBJZmator+G9d4zU9DTKCVF1hz9N7KBv6rv8YUc5KwTVW3ZiEMzR1NYKPDZoDm0 ClQ7sKz8NRK5Eh4VWyadE5VSKXU0H1iZrfjf2a2HfwAE/feWFOAZFY6BkuXNArbeYO ySqDiSHoxaKAPR98LVvt9fgFoU/nTBW/zfg0/jBU= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x1DDRVNH117469 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 13 Feb 2019 07:27:31 -0600 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Wed, 13 Feb 2019 07:27:31 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Wed, 13 Feb 2019 07:27:31 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x1DDRGZe016688; Wed, 13 Feb 2019 07:27:29 -0600 From: Kishon Vijay Abraham I To: Murali Karicheri , Lorenzo Pieralisi CC: Kishon Vijay Abraham I , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , , , Subject: [PATCH v3 4/9] PCI: keystone: Use hwirq to get the MSI IRQ number offset Date: Wed, 13 Feb 2019 18:56:24 +0530 Message-ID: <20190213132629.24790-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190213132629.24790-1-kishon@ti.com> References: <20190213132629.24790-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ks_pcie_msi_irq_handler() uses 'virq' to get the IRQ number offset. This offset is used to get the correct MSI_IRQ_STATUS register corresponding to the IRQ line that raised the interrupt. There is no guarantee that 'virq' assigned for consecutive hardware IRQ will be contiguous. And this might get us an incorrect IRQ number offset. Fix it here by using 'hwirq' to get the IRQ number offset. Since we don't store the 'virq' numbers of all the IRQ numbers, stop checking if irq count is greater than MAX_MSI_HOST_IRQS and remove MAX_MSI_HOST_IRQS. Link: https://lkml.kernel.org/r/bb081d21-7c03-0357-4294-7e92d95d838c@arm.com Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 24 ++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index d35ac712a9f8..90d64507acd0 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -74,7 +74,6 @@ #define ERR_IRQ_ALL (ERR_AER | ERR_AXI | ERR_CORR | \ ERR_NONFATAL | ERR_FATAL | ERR_SYS) -#define MAX_MSI_HOST_IRQS 8 /* PCIE controller device IDs */ #define PCIE_RC_K2HK 0xb008 #define PCIE_RC_K2E 0xb009 @@ -90,7 +89,7 @@ struct keystone_pcie { int legacy_host_irq; struct device_node *legacy_intc_np; - int msi_host_irqs[MAX_MSI_HOST_IRQS]; + int msi_host_irq; int num_lanes; u32 num_viewport; struct phy **phy; @@ -553,9 +552,9 @@ static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { - unsigned int irq = irq_desc_get_irq(desc); + unsigned int irq = desc->irq_data.hwirq; struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc); - u32 offset = irq - ks_pcie->msi_host_irqs[0]; + u32 offset = irq - ks_pcie->msi_host_irq; struct dw_pcie *pci = ks_pcie->pci; struct device *dev = pci->dev; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -606,6 +605,7 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) struct device *dev = ks_pcie->pci->dev; struct device_node *np = ks_pcie->np; struct device_node *intc_np; + struct irq_data *irq_data; int irq_count, irq, ret, i; if (!IS_ENABLED(CONFIG_PCI_MSI)) @@ -624,19 +624,21 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) goto err; } - if (irq_count > MAX_MSI_HOST_IRQS) { - dev_warn(dev, "Too many MSI interrupt lines defined %u\n", - irq_count); - irq_count = MAX_MSI_HOST_IRQS; - } - for (i = 0; i < irq_count; i++) { irq = irq_of_parse_and_map(intc_np, i); if (!irq) { ret = -EINVAL; goto err; } - ks_pcie->msi_host_irqs[i] = irq; + + if (!ks_pcie->msi_host_irq) { + irq_data = irq_get_irq_data(irq); + if (!irq_data) { + ret = -EINVAL; + goto err; + } + ks_pcie->msi_host_irq = irq_data->hwirq; + } irq_set_chained_handler_and_data(irq, ks_pcie_msi_irq_handler, ks_pcie);