From patchwork Mon Mar 18 13:12:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Leizhen \(ThunderTown\)" X-Patchwork-Id: 160491 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp2643903jad; Mon, 18 Mar 2019 06:14:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqy1BuUslPbJuZzdm6l/7XB1ObcVI71e1BmB+3g5L/ck+0uMJmRLk1Zpdd6BnIaTlBEEFeAW X-Received: by 2002:a63:ee58:: with SMTP id n24mr17356275pgk.247.1552914877184; Mon, 18 Mar 2019 06:14:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1552914877; cv=none; d=google.com; s=arc-20160816; b=bF6j6XoheX0W8xX3bZrsHdjSHIWiv8z23J/Gnzxe/n+HwkaVcnujdiL7Kzhk0++KFK CPxInCnymPZfQL+QwrGYipSwzXEQjG9c/9zdnrrCe96Ilj25Fi0Lr3FzT2ChVuv0l4pH HxDFtoTw4IiA3biu/OTWpKIkJDTtgjMwZ3vznPXtxgApvYd34W+yt0ZXX/1Slv4lafLI GuLaw0dmI/OPH9CtedhkF/J6EOEbSxRLY7ImmOZw5pBGvc0Gfvd82PolaMqcjxiYp3mu Q4zzr0xX2MgrUWaZSnMAM9EJTqCs94TrDDPade9lhtGvBeRQDdXoqqNF4fcALk6fsYf1 jwYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=1shit6Owa0u7qzITRLCxafF+YcwlIuNBM5U/wupQwYo=; b=ajM2poSUxCAGsezK/2PCgQ9YFY5A1ue6G1WWnwz5OnezboPPRnUNyyn6HnfuaD9J6b mP6BT2PW/wlA6na164B0Xp5zFu+IIL3IhHXN0al6poUYeOniiDufUk5Ep6VAevy62JQV wxuci7wZaDUyA2Syt1pVCXygi6KSZpZasn2sCvAATwEwSz7u6XOP5B7Ya3QMkhC0OqJE 995J9SP30pL5jCbqwITlUtuiLq5clMVQ1evBFS3oY0gmt7MoXcIGb619ZvrU6bieccWo UxVyx/nYJntlVDTzLzXf1RhzlHkEHRs3urF1S486rh9OxFWI1m/g4b+c+GTYKAublqrs 6Ghw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y8si9183332plp.385.2019.03.18.06.14.36; Mon, 18 Mar 2019 06:14:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727457AbfCRNOa (ORCPT + 31 others); Mon, 18 Mar 2019 09:14:30 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:52242 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726093AbfCRNO3 (ORCPT ); Mon, 18 Mar 2019 09:14:29 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C67FACB25BD9615062DA; Mon, 18 Mar 2019 21:14:27 +0800 (CST) Received: from HGHY1l002753561.china.huawei.com (10.177.23.164) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.408.0; Mon, 18 Mar 2019 21:14:16 +0800 From: Zhen Lei To: Jean-Philippe Brucker , Robin Murphy , Will Deacon , Joerg Roedel , linux-arm-kernel , iommu , linux-kernel CC: Zhen Lei Subject: [PATCH v2 1/2] iommu/arm-smmu-v3: make sure the stale caching of L1STD are invalid Date: Mon, 18 Mar 2019 21:12:42 +0800 Message-ID: <20190318131243.20716-2-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.19.2.windows.1 In-Reply-To: <20190318131243.20716-1-thunder.leizhen@huawei.com> References: <20190318131243.20716-1-thunder.leizhen@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.164] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org After the content of L1STD(Level 1 Stream Table Descriptor) in DDR has been modified, should make sure the cached copies be invalidated. Signed-off-by: Zhen Lei --- drivers/iommu/arm-smmu-v3.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 1.8.3 diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c index d3880010c6cfc8c..9b6afa8e69f70f6 100644 --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c @@ -1071,13 +1071,14 @@ static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, *dst = cpu_to_le64(val); } -static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +static void __arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, + u32 sid, bool leaf) { struct arm_smmu_cmdq_ent cmd = { .opcode = CMDQ_OP_CFGI_STE, .cfgi = { .sid = sid, - .leaf = true, + .leaf = leaf, }, }; @@ -1085,6 +1086,16 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) arm_smmu_cmdq_issue_sync(smmu); } +static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __arm_smmu_sync_ste_for_sid(smmu, sid, true); +} + +static void arm_smmu_sync_std_for_sid(struct arm_smmu_device *smmu, u32 sid) +{ + __arm_smmu_sync_ste_for_sid(smmu, sid, false); +} + static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid, __le64 *dst, struct arm_smmu_strtab_ent *ste) { @@ -1232,6 +1243,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) arm_smmu_init_bypass_stes(desc->l2ptr, 1 << STRTAB_SPLIT); arm_smmu_write_strtab_l1_desc(strtab, desc); + arm_smmu_sync_std_for_sid(smmu, sid); return 0; }