From patchwork Thu Mar 21 23:05:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 160829 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp140140jan; Thu, 21 Mar 2019 16:06:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqxQEG0wjXEkH09IVvoJyD1apl7gYNUdty9oyexP4OSxGbikab5KcqZYQ1oKLWVRqlsp1H4D X-Received: by 2002:a17:902:142:: with SMTP id 60mr6144170plb.191.1553209590589; Thu, 21 Mar 2019 16:06:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553209590; cv=none; d=google.com; s=arc-20160816; b=a7yb19RyJFArATx1ojl6C2UxG0CoPnmEuzdlcs00LZQnlZHys0WDryQUJxIrbL89w6 9Vpy14QLemQOS4+lPio3buzCV2jsOaHNFnpsapzjxDbE/XmOx8e0DZCXsXoqH/X+G2Ig jxQClJHF+GuE9nQ0SKCPRieY8R1/d2pHv27fjsLA7se2I2/sllhkWz79C1hJybC/Z7o1 +ep2/WEYYKQxn1zV5MQyfFpv3NHNgBx3ODDIpkwkpudYJUu/XK3UMq9hRYp3UMh1z4SO YvHphmsumQAqqjMewrUJIaq+L0ke6nMY4TbPqwswpClnBAFBfk+g3iHoVGWICUZios+3 GyeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=fYAjJRzg85f5sfKIQ/o/jlK9Tre7G8lj8UdY1P3XXCU=; b=tF0qjh2aZ9VyBgC+Q8D3PGB5fqzYeBGGih8cdB4b+CdsuDGPYh76wYCG+BjR+pmVTe PVhGcLsgLJmsdKXZvDaqANLbb3CWB0JmngMfDvmfhuJsoOLbR7mi24wfDOycCpDUtbz/ 6kgwocik194dI29RR8tpzAEGzGDyVjaU/XXR8guO1Z1IYMjcVtNsJlUc8voIrDEHhlsQ vuzJBH1fPQuoC26rcw60VucM//fhnt/F1n1IqRC+6iHKmakmxlhtfc6kbDEsKo4StSVg r2zBr3gZL4GPpZUJjFOoGUWLgYbIi6YvDGzdZZcqq4n1/5gr2h+TasuYm7nZqb1OGKnB LASg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f6si5491856plr.411.2019.03.21.16.06.30; Thu, 21 Mar 2019 16:06:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727532AbfCUXG2 (ORCPT + 31 others); Thu, 21 Mar 2019 19:06:28 -0400 Received: from foss.arm.com ([217.140.101.70]:35832 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727488AbfCUXGX (ORCPT ); Thu, 21 Mar 2019 19:06:23 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4CC0E15BE; Thu, 21 Mar 2019 16:06:23 -0700 (PDT) Received: from beelzebub.austin.arm.com (mammon-tx2.austin.arm.com [10.118.29.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9C4393F614; Thu, 21 Mar 2019 16:06:22 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will.deacon@arm.com, marc.zyngier@arm.com, suzuki.poulose@arm.com, Dave.Martin@arm.com, shankerd@codeaurora.org, julien.thierry@arm.com, mlangsdo@redhat.com, stefan.wahren@i2e.com, Andre.Przywara@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton , Andre Przywara , Stefan Wahren Subject: [PATCH v6 09/10] arm64: add sysfs vulnerability show for speculative store bypass Date: Thu, 21 Mar 2019 18:05:56 -0500 Message-Id: <20190321230557.45107-10-jeremy.linton@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190321230557.45107-1-jeremy.linton@arm.com> References: <20190321230557.45107-1-jeremy.linton@arm.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Return status based on ssbd_state and the arm64 SSBS feature. If the mitigation is disabled, or the firmware isn't responding then return the expected machine state based on a new blacklist of known vulnerable cores. Signed-off-by: Jeremy Linton Reviewed-by: Andre Przywara Tested-by: Stefan Wahren --- arch/arm64/kernel/cpu_errata.c | 44 ++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) -- 2.20.1 diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 6958dcdabf7d..172ffbabd597 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -278,6 +278,7 @@ static int detect_harden_bp_fw(void) DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required); int ssbd_state __read_mostly = ARM64_SSBD_KERNEL; +static bool __ssb_safe = true; static const struct ssbd_options { const char *str; @@ -386,6 +387,9 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + if (is_midr_in_range_list(read_cpuid_id(), entry->midr_range_list)) + __ssb_safe = false; + if (this_cpu_has_cap(ARM64_SSBS)) { required = false; goto out_printmsg; @@ -419,12 +423,14 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, ssbd_state = ARM64_SSBD_UNKNOWN; return false; + /* machines with mixed mitigation requirements must not return this */ case SMCCC_RET_NOT_REQUIRED: pr_info_once("%s mitigation not required\n", entry->desc); ssbd_state = ARM64_SSBD_MITIGATED; return false; case SMCCC_RET_SUCCESS: + __ssb_safe = false; required = true; break; @@ -474,6 +480,16 @@ static bool has_ssbd_mitigation(const struct arm64_cpu_capabilities *entry, return required; } +/* known vulnerable cores */ +static const struct midr_range arm64_ssb_cpus[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), + {}, +}; + static void __maybe_unused cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused) { @@ -769,6 +785,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_SSBD, .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, .matches = has_ssbd_mitigation, + .midr_range_list = arm64_ssb_cpus, }, #ifdef CONFIG_ARM64_ERRATUM_1188873 { @@ -807,3 +824,30 @@ ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, return sprintf(buf, "Vulnerable\n"); } + +ssize_t cpu_show_spec_store_bypass(struct device *dev, + struct device_attribute *attr, char *buf) +{ + /* + * Two assumptions: First, ssbd_state reflects the worse case + * for heterogeneous machines, and that if SSBS is supported its + * supported by all cores. + */ + switch (ssbd_state) { + case ARM64_SSBD_MITIGATED: + return sprintf(buf, "Not affected\n"); + + case ARM64_SSBD_KERNEL: + case ARM64_SSBD_FORCE_ENABLE: + if (cpus_have_cap(ARM64_SSBS)) + return sprintf(buf, "Not affected\n"); + if (IS_ENABLED(CONFIG_ARM64_SSBD)) + return sprintf(buf, + "Mitigation: Speculative Store Bypass disabled\n"); + } + + if (__ssb_safe) + return sprintf(buf, "Not affected\n"); + + return sprintf(buf, "Vulnerable\n"); +}