From patchwork Tue Apr 30 11:38:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg Kroah-Hartman X-Patchwork-Id: 163104 Delivered-To: patch@linaro.org Received: by 2002:a92:7e86:0:0:0:0:0 with SMTP id q6csp3118564ill; Tue, 30 Apr 2019 04:49:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqxP/D4C/z9uqnN7OaekCKtu6HmOpldE9QDr5BcAl3rflq3kXs7Tvvh9B/P3AD6h1ydMjDRh X-Received: by 2002:a63:2c06:: with SMTP id s6mr66024456pgs.245.1556624977913; Tue, 30 Apr 2019 04:49:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1556624977; cv=none; d=google.com; s=arc-20160816; b=lgz2jVU3L2iP7JdVgroCuOVJtxKtrfLDGK2kmE7Kx4TuESet3FWxODAwiTD7fL5Quv c0YKxRlNeRZbg6KmdDuvEXU6HEMJLqobuVhvhmTACDdkuTMtpKRV6cWAq92S2s6s1pNA sAbzG70kxvDoT6iXqdbTsxC1+e/JNcv1k66tLrCAEweQVSYDpxgqyKrpz+vFM86BsUce fmMEk6yWHqGibYdrV4GfFo6TsGuSAgG3BHgJuxKmAErR7OZVFh4nM5BA6Jpjgf+eWYSi 7Waz8btv+EiYJVFBHzOn3tWp5smVz9GxvHHQ54uKOtcEUtjAPn8sJPYg5wIn9sWQyISR 5sPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :user-agent:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8TRkLvBA98VYvbFo+K1En4i1cTrCXVSWbu/kS90xncw=; b=M/711PNlo8Qd+4q3MpfqR2RwVOrGUu7zjBFHwPRDcQTnUi8KBxl00BZq76DDM/8riS 8cpETYF2n/DD+weyoZ3nBI0KaNxCgZonEgronaWy7bGBF3QRDhtcuBXgGl564qZDefuV bzcRj8fV9UpidU7m1VneSYM3cKj1VQoBhgGw4VLCJbfq/ga2qXCvZEymOvoscDHMLbTZ tJ/Vn2VeDMKf2HZkc9WdUH1SHlZWjL5zgQizirpyUn5gN92ZeFWYJRN6FA2/LPeja5qn CbVeUt8Ty/a3h1LxRqY32ZzJEih5U/VNifQpdcr40JOYaatdyuRi9j9xwBfC2AOiDk0l GPSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ApLgYCaU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h126si35209237pgc.508.2019.04.30.04.49.37; Tue, 30 Apr 2019 04:49:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=ApLgYCaU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731018AbfD3Ltf (ORCPT + 30 others); Tue, 30 Apr 2019 07:49:35 -0400 Received: from mail.kernel.org ([198.145.29.99]:36080 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730709AbfD3Ltb (ORCPT ); Tue, 30 Apr 2019 07:49:31 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4F84921734; Tue, 30 Apr 2019 11:49:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1556624970; bh=9wjh8KhDFWxat4RFS8FnsuU4lCY2MRrx7waCkkCQFj8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ApLgYCaUFnLhuRsBl3zlGbpDChZLk2FFww1ChjRkBjFJiTy9tmiMtEWJ1dm/nfFfz fJ3gFYYRChYK/PSRCKOF9jmbv9eJJcSeItrh+ygEUNqsfon+EUoiz1jGfA9HKFZtpp OPh/8J9OqgV3Ap6Qh3loMKEw1/WD08CAwDQLUHLg= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Marc Zyngier , Ard Biesheuvel , Russell King Subject: [PATCH 5.0 40/89] ARM: 8857/1: efi: enable CP15 DMB instructions before cleaning the cache Date: Tue, 30 Apr 2019 13:38:31 +0200 Message-Id: <20190430113611.689521185@linuxfoundation.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190430113609.741196396@linuxfoundation.org> References: <20190430113609.741196396@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ard Biesheuvel commit e17b1af96b2afc38e684aa2f1033387e2ed10029 upstream. The EFI stub is entered with the caches and MMU enabled by the firmware, and once the stub is ready to hand over to the decompressor, we clean and disable the caches. The cache clean routines use CP15 barrier instructions, which can be disabled via SCTLR. Normally, when using the provided cache handling routines to enable the caches and MMU, this bit is enabled as well. However, but since we entered the stub with the caches already enabled, this routine is not executed before we call the cache clean routines, resulting in undefined instruction exceptions if the firmware never enabled this bit. So set the bit explicitly in the EFI entry code, but do so in a way that guarantees that the resulting code can still run on v6 cores as well (which are guaranteed to have CP15 barriers enabled) Cc: # v4.9+ Acked-by: Marc Zyngier Signed-off-by: Ard Biesheuvel Signed-off-by: Russell King Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/compressed/head.S | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -1438,7 +1438,21 @@ ENTRY(efi_stub_entry) @ Preserve return value of efi_entry() in r4 mov r4, r0 - bl cache_clean_flush + + @ our cache maintenance code relies on CP15 barrier instructions + @ but since we arrived here with the MMU and caches configured + @ by UEFI, we must check that the CP15BEN bit is set in SCTLR. + @ Note that this bit is RAO/WI on v6 and earlier, so the ISB in + @ the enable path will be executed on v7+ only. + mrc p15, 0, r1, c1, c0, 0 @ read SCTLR + tst r1, #(1 << 5) @ CP15BEN bit set? + bne 0f + orr r1, r1, #(1 << 5) @ CP15 barrier instructions + mcr p15, 0, r1, c1, c0, 0 @ write SCTLR + ARM( .inst 0xf57ff06f @ v7+ isb ) + THUMB( isb ) + +0: bl cache_clean_flush bl cache_off @ Set parameters for booting zImage according to boot protocol