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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:41 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period Date: Wed, 26 Jun 2019 16:46:44 +0200 Message-Id: <20190626144651.16742-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko The of_clk structure has a period field that is set up initially by timer_of_clk_init(), that period value need to be adjusted for a case of TIMER1-9 that are running at a fixed rate that doesn't match the clock's rate. Note that the period value is currently used only by some of the clocksource drivers internally and hence this is just a minor cleanup change that doesn't fix anything. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f172a57cc5fe..41257f89a216 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -73,9 +73,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + unsigned long period = timer_of_period(to_timer_of(evt)); - writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), reg_base + TIMER_PTV); return 0; @@ -299,6 +299,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->of_clk.period = rate / HZ; cpu_to->of_clk.rate = rate; irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);