From patchwork Wed Oct 23 10:13:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 177264 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp503518ill; Wed, 23 Oct 2019 03:14:21 -0700 (PDT) X-Google-Smtp-Source: APXvYqzN/00Prz1EBG412Yi9O6kDK7hdrWusqSQYAy/Qt8wxkK083LksIzKnF0tYUcQthF2cHQjY X-Received: by 2002:a17:906:4ec2:: with SMTP id i2mr16041829ejv.330.1571825661846; Wed, 23 Oct 2019 03:14:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571825661; cv=none; d=google.com; s=arc-20160816; b=GkPTYTi7XPWOmwYvcfW3d0X+LEMqL9OrIQmG78GD20ASHrY0kE+SO0bZO2iSxa8hLE sR8CJqLmvHYWQVFmflmoNH95Sdjfnxm+hqbtaA6Zxv1xeF3kOuuPeJKfG674qNBvQwoO vkmagZMtC8ZizYIwqlO3blXLXBwOvcC9eiNcum/1P9IF4lILzdfoD9APeOVeQE2+tH13 VaycujuB1OEdCp+/or+jTf5Rr9EC18nl3Z+X8h/5Q2G7osKJrGttIsItS70loRXlXdBv jVmsc919/6uHITNqryFZWb7/wXesaj5HWEthtvGEVyOAoghY6c6VTvP+QCpgVnk0b4Fx Cf4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=p6rmdgyuZkZnMv1gtd9j/dcdGBFn8Hu0XYVI4BRp4O0=; b=Gb9vtZiJwjIjETd7d8iiyp0irUp8EN7HF/QjF/NKC6y7O3jfZ32SacVBEOoICgEiS0 GkqtBaAayXc9wihAIX/x0fOXcPIjeC/bybjHQK/WJ7gNIGL3tIYuw3KFCtobaJdZqHtP XnYOxxf4piTKN62ZJ5WRvstfNzMDIP69o/yfAky31M2YdPq6RJ0NUE7qC1iq05wasmV4 yd6BJ4PCnn9AS+apo8lWu4oDqP7r8sjX9yvBFj8eMBtK6KnhXZT1pOw+yM09yu8sYM/0 HUk+uaD5wgjlbLTid/zJU8jp28kjyu/yUwORsBXerqCulLO1rjjdkDgfAsJWdprIty+G tZAw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y26si13458681edv.134.2019.10.23.03.14.21; Wed, 23 Oct 2019 03:14:21 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404360AbfJWKOT (ORCPT + 26 others); Wed, 23 Oct 2019 06:14:19 -0400 Received: from mx2.suse.de ([195.135.220.15]:53804 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2391029AbfJWKNa (ORCPT ); Wed, 23 Oct 2019 06:13:30 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 40CC8B513; Wed, 23 Oct 2019 10:13:28 +0000 (UTC) From: =?utf-8?q?Andreas_F=C3=A4rber?= To: linux-realtek-soc@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Andreas_F=C3=A4rber?= , Philipp Zabel , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH v2 02/11] dt-bindings: reset: Add Realtek RTD1195 Date: Wed, 23 Oct 2019 12:13:08 +0200 Message-Id: <20191023101317.26656-3-afaerber@suse.de> X-Mailer: git-send-email 2.16.4 In-Reply-To: <20191023101317.26656-1-afaerber@suse.de> References: <20191023101317.26656-1-afaerber@suse.de> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a header with symbolic reset indices for Realtek RTD1195 SoC. Naming was derived from BSP register description headers. Signed-off-by: Andreas Färber --- v2: New include/dt-bindings/reset/realtek,rtd1195.h | 74 +++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 include/dt-bindings/reset/realtek,rtd1195.h -- 2.16.4 diff --git a/include/dt-bindings/reset/realtek,rtd1195.h b/include/dt-bindings/reset/realtek,rtd1195.h new file mode 100644 index 000000000000..27902abf935b --- /dev/null +++ b/include/dt-bindings/reset/realtek,rtd1195.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Realtek RTD1195 reset controllers + * + * Copyright (c) 2017 Andreas Färber + */ +#ifndef DT_BINDINGS_RESET_RTD1195_H +#define DT_BINDINGS_RESET_RTD1195_H + +/* soft reset 1 */ +#define RTD1195_RSTN_MISC 0 +#define RTD1195_RSTN_RNG 1 +#define RTD1195_RSTN_USB3_POW 2 +#define RTD1195_RSTN_GSPI 3 +#define RTD1195_RSTN_USB3_P0_MDIO 4 +#define RTD1195_RSTN_VE_H265 5 +#define RTD1195_RSTN_USB 6 +#define RTD1195_RSTN_USB_PHY0 8 +#define RTD1195_RSTN_USB_PHY1 9 +#define RTD1195_RSTN_HDMIRX 11 +#define RTD1195_RSTN_HDMI 12 +#define RTD1195_RSTN_ETN 14 +#define RTD1195_RSTN_AIO 15 +#define RTD1195_RSTN_GPU 16 +#define RTD1195_RSTN_VE_H264 17 +#define RTD1195_RSTN_VE_JPEG 18 +#define RTD1195_RSTN_TVE 19 +#define RTD1195_RSTN_VO 20 +#define RTD1195_RSTN_LVDS 21 +#define RTD1195_RSTN_SE 22 +#define RTD1195_RSTN_DCU 23 +#define RTD1195_RSTN_DC_PHY 24 +#define RTD1195_RSTN_CP 25 +#define RTD1195_RSTN_MD 26 +#define RTD1195_RSTN_TP 27 +#define RTD1195_RSTN_AE 28 +#define RTD1195_RSTN_NF 29 +#define RTD1195_RSTN_MIPI 30 + +/* soft reset 2 */ +#define RTD1195_RSTN_ACPU 0 +#define RTD1195_RSTN_VCPU 1 +#define RTD1195_RSTN_PCR 9 +#define RTD1195_RSTN_CR 10 +#define RTD1195_RSTN_EMMC 11 +#define RTD1195_RSTN_SDIO 12 +#define RTD1195_RSTN_I2C_5 18 +#define RTD1195_RSTN_RTC 20 +#define RTD1195_RSTN_I2C_4 23 +#define RTD1195_RSTN_I2C_3 24 +#define RTD1195_RSTN_I2C_2 25 +#define RTD1195_RSTN_I2C_1 26 +#define RTD1195_RSTN_UR1 28 + +/* soft reset 3 */ +#define RTD1195_RSTN_SB2 0 + +/* iso soft reset */ +#define RTD1195_ISO_RSTN_VFD 0 +#define RTD1195_ISO_RSTN_IR 1 +#define RTD1195_ISO_RSTN_CEC0 2 +#define RTD1195_ISO_RSTN_CEC1 3 +#define RTD1195_ISO_RSTN_DP 4 +#define RTD1195_ISO_RSTN_CBUSTX 5 +#define RTD1195_ISO_RSTN_CBUSRX 6 +#define RTD1195_ISO_RSTN_EFUSE 7 +#define RTD1195_ISO_RSTN_UR0 8 +#define RTD1195_ISO_RSTN_GMAC 9 +#define RTD1195_ISO_RSTN_GPHY 10 +#define RTD1195_ISO_RSTN_I2C_0 11 +#define RTD1195_ISO_RSTN_I2C_6 12 +#define RTD1195_ISO_RSTN_CBUS 13 + +#endif