From patchwork Thu Dec 14 15:33:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Viresh Kumar X-Patchwork-Id: 121979 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp6960961qgn; Thu, 14 Dec 2017 07:34:51 -0800 (PST) X-Google-Smtp-Source: ACJfBoucRTIDfwouzX7b653qNromOvNtpJK7cU5U2TCyKQS7L7cGNcah+8+J0U79zsBaFRKnRRHu X-Received: by 10.84.252.137 with SMTP id y9mr9737442pll.153.1513265690847; Thu, 14 Dec 2017 07:34:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513265690; cv=none; d=google.com; s=arc-20160816; b=LOXXaznWkm8HZYjVD3uo03V+cfjfQcUAtY7c8xHPE7yzYhJLqu7v2eUYegsAjwLdaT G9sJA+CNIWxYu7+RMND2WaYaiwvhCa5pIu1fUmxZGL+RRO7Smbapps3z777Cg5aDiCyI fjFUI/PfLE1izpZN7/KdKxsvqSpGlGEzDrZJ5mi0kqyqLNejuI7SWyr8e+JDOk9QJ4xJ zlgxaXjWXbRHaMbMF5Fe/g5m5tYIF9Eym6Lh3/3A1/x7//TJdYC+lrIXJtriNWhDouuh vp7XsWkFvWjH2Q0aQ8ZZN9nGwseKicKTxOOsYiyc3ea3q67HMC2PEUzk039Hsz2nGHVN caaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=SjXMPtCgr7kmgW6Sc3OPuAZH24KsIrVGddQxvD6R5y0=; b=zrWFD6YDP8XeFXzfIBjphkWe5CE1joURQRJeDo+ZgekV188Q/ZNwPJR4QaDNN+/h8q cNy35j8aB1kX4OsSTAlsArjNEM0XEvEbWROx882E/SNx0yNs+q8qlsJLCGJtrBpFJ8V/ KOrjJJQrzXiNklU3i0ePdY5goTfMf6chliZoiRAKo6l57ak3qnrLf1s6GfyfNUFBHzna Js4orz32SN922sVu77nfmXCFYNpJ+DHH9wbHfc/isu6nXgoEM0sjJcS0vtL1/88s8o2w ntw7CMSBRjP6XspgGWVkuUl+Vlj5M6K6+WE5ZHbh8yhr1S6xqe8s4KNUBnHe/SoZLhCr 72Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LI+oPMH4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c26si3412776pfh.105.2017.12.14.07.34.50; Thu, 14 Dec 2017 07:34:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LI+oPMH4; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753550AbdLNPeq (ORCPT + 19 others); Thu, 14 Dec 2017 10:34:46 -0500 Received: from mail-pf0-f196.google.com ([209.85.192.196]:34356 "EHLO mail-pf0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753488AbdLNPeX (ORCPT ); Thu, 14 Dec 2017 10:34:23 -0500 Received: by mail-pf0-f196.google.com with SMTP id a90so3862401pfk.1 for ; Thu, 14 Dec 2017 07:34:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=SjXMPtCgr7kmgW6Sc3OPuAZH24KsIrVGddQxvD6R5y0=; b=LI+oPMH4R9c2x7tUfCZ45Gcatv9F0d5zcKlhxNoKKdVDMP1kevEWhK+MOKho5LFrCg AEclw8sYgQTLaRLitS37tHsVfiDJjW025jP7RVTRd2fx+hcphXbvvBiTkoV6/P51ZjsW gApQPA0yE4y9lbbZ8Wjud7nUtxbIKjNwNMV14= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=SjXMPtCgr7kmgW6Sc3OPuAZH24KsIrVGddQxvD6R5y0=; b=ay02YL92gSjlCPsMYG8Ve64ikj4HeboMf3hB9a1qvXA+Dbx8n+GFlDLlYdtCd9ysR8 UTu3izFHjojZN8Gkc1K3TVAmZCRjFSoOqqzS4Y8rDvO5NatYmepZLpuIAijU50HvrO03 yyee54OYQF5MXyvYBm1sROkr1Sgm+aehUlRZtobN2uluHzlgEhAIww/Kp4QaGKYW7A9P bcxpVil9HzyHxElpgIVzsVFaJ/py/QlnoN5aOZMF13JqpvQPzU6Mp7SvfYJG85pLU4xp DPiq+rfp+KO/j6exbD583JGPJR68SvDKNfMQYHC1pB+RGjskHdzzUwVFoK6aORpBlG+N qqRw== X-Gm-Message-State: AKGB3mJmBo9pNem1rm+AAiVEUffLcqkdZPTwokdTi1EFuuPLLgR7tAPM i8woY98KEQ4KlVG7k4onVHFbmw== X-Received: by 10.101.81.72 with SMTP id g8mr8930870pgq.135.1513265662413; Thu, 14 Dec 2017 07:34:22 -0800 (PST) Received: from localhost ([122.172.99.7]) by smtp.gmail.com with ESMTPSA id b25sm9241551pfd.182.2017.12.14.07.34.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Dec 2017 07:34:21 -0800 (PST) From: Viresh Kumar To: Greg Kroah-Hartman Cc: Viresh Kumar , Vincent Guittot , Stephen Boyd , Rajendra Nayak , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robdclark@gmail.com, s.hauer@pengutronix.de, l.stach@pengutronix.de, shawnguo@kernel.org, fabio.estevam@nxp.com, nm@ti.com, xuwei5@hisilicon.com, robh+dt@kernel.org Subject: [PATCH V5 11/13] boot_constraint: Add Qualcomm display controller constraints Date: Thu, 14 Dec 2017 21:03:18 +0530 Message-Id: <22b3eec1377cc64242bede04f03bb65b8d2ba00a.1513264961.git.viresh.kumar@linaro.org> X-Mailer: git-send-email 2.15.0.194.g9af6a3dea062 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rajendra Nayak This sets boot constraints for the display controller used on Qualcomm dragonboard 410c. The display controlled is enabled by the bootloader to show a flash screen during kernel boot. The handover to kernel should be without any glitches on the screen.The resources of the display controller (like regulators) are shared with other peripherals, which may reconfigure those resources before the display driver comes up. The same problem can happen if the display driver probes first, as the constraints of the other devices (sharing same resources with display controller) may not be honored anymore by the kernel. Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig.platforms | 1 + drivers/boot_constraint/Makefile | 1 + drivers/boot_constraint/qcom.c | 122 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) create mode 100644 drivers/boot_constraint/qcom.c -- 2.15.0.194.g9af6a3dea062 diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index a586ed728393..b514327290ca 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -136,6 +136,7 @@ config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB select PINCTRL + select DEV_BOOT_CONSTRAINT help This enables support for the ARMv8 based Qualcomm chipsets. diff --git a/drivers/boot_constraint/Makefile b/drivers/boot_constraint/Makefile index f3e123b5d854..7b6b5966c908 100644 --- a/drivers/boot_constraint/Makefile +++ b/drivers/boot_constraint/Makefile @@ -4,3 +4,4 @@ obj-y := clk.o deferrable_dev.o core.o pm.o supply.o obj-$(CONFIG_ARCH_HISI) += hikey.o obj-$(CONFIG_ARCH_MXC) += imx.o +obj-$(CONFIG_ARCH_QCOM) += qcom.o diff --git a/drivers/boot_constraint/qcom.c b/drivers/boot_constraint/qcom.c new file mode 100644 index 000000000000..0498f464da05 --- /dev/null +++ b/drivers/boot_constraint/qcom.c @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * This sets up Dragonboard 410c constraints on behalf of the bootloader, which + * uses display controller to display a flash screen during system boot. + * + * Copyright (C) 2017 Linaro. + * Viresh Kumar + * Rajendra Nayak + */ + +#include +#include +#include +#include + +static struct dev_boot_constraint_clk_info iface_clk_info = { + .name = "iface_clk", +}; + +static struct dev_boot_constraint_clk_info bus_clk_info = { + .name = "bus_clk", +}; + +static struct dev_boot_constraint_clk_info core_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info vsync_clk_info = { + .name = "vsync_clk", +}; + +static struct dev_boot_constraint_clk_info esc0_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info byte_clk_info = { + .name = "byte_clk", +}; + +static struct dev_boot_constraint_clk_info pixel_clk_info = { + .name = "pixel_clk", +}; + +static struct dev_boot_constraint_supply_info vdda_info = { + .name = "vdda" +}; + +static struct dev_boot_constraint_supply_info vddio_info = { + .name = "vddio" +}; + +static struct dev_boot_constraint constraints_mdss[] = { + { + .type = DEV_BOOT_CONSTRAINT_PM, + .data = NULL, + }, +}; + +static struct dev_boot_constraint constraints_mdp[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &iface_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &bus_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &core_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &vsync_clk_info, + }, +}; + +static struct dev_boot_constraint constraints_dsi[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &esc0_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &byte_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &pixel_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vdda_info, + + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vddio_info, + }, +}; + +static struct dev_boot_constraint_of constraints[] = { + { + .compat = "qcom,mdss", + .constraints = constraints_mdss, + .count = ARRAY_SIZE(constraints_mdss), + }, { + .compat = "qcom,mdp5", + .constraints = constraints_mdp, + .count = ARRAY_SIZE(constraints_mdp), + }, { + .compat = "qcom,mdss-dsi-ctrl", + .constraints = constraints_dsi, + .count = ARRAY_SIZE(constraints_dsi), + }, +}; + +static int __init qcom_constraints_init(void) +{ + /* Only Dragonboard 410c is supported for now */ + if (!of_machine_is_compatible("qcom,apq8016-sbc")) + return 0; + + dev_boot_constraint_add_deferrable_of(constraints, + ARRAY_SIZE(constraints)); + + return 0; +} +subsys_initcall(qcom_constraints_init);